git.sur5r.net Git - u-boot/blob - board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <asm/errno.h>
  14 #include <spl.h>
  15 #include <usb.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mux.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/emif.h>
  23 #include "../common/board_detect.h"
  24 #include "board.h"
  25 #include <power/pmic.h>
  26 #include <power/tps65218.h>
  27 #include <power/tps62362.h>
  28 #include <miiphy.h>
  29 #include <cpsw.h>
  30 #include <linux/usb/gadget.h>
  31 #include <dwc3-uboot.h>
  32 #include <dwc3-omap-uboot.h>
  33 #include <ti-usb-phy-uboot.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  38
  39 /*
  40  * Read header information from EEPROM into global structure.
  41  */
  42 static inline int __maybe_unused read_eeprom(void)
  43 {
  44         return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
  45 }
  46
  47 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  48
  49 #define NUM_OPPS        6
  50
  51 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  52         {       /* 19.2 MHz */
  53                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  54                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  55                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  56                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  57                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  58                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  59         },
  60         {       /* 24 MHz */
  61                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  62                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  63                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  64                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  65                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  66                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  67         },
  68         {       /* 25 MHz */
  69                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  70                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  71                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  72                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  73                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  74                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  75         },
  76         {       /* 26 MHz */
  77                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  78                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  79                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  80                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  81                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  82                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  83         },
  84 };
  85
  86 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  87                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  88                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  89                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  90                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
  91 };
  92
  93 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  94                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
  95                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
  96                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
  97                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
  98 };
  99
 100 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 101                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 102                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 103                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 104                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 105 };
 106
 107 const struct dpll_params gp_evm_dpll_ddr = {
 108                 50, 2, 1, -1, 2, -1, -1};
 109
 110 static const struct dpll_params idk_dpll_ddr = {
 111         400, 23, 1, -1, 2, -1, -1
 112 };
 113
 114 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 115         0x00500050,
 116         0x00350035,
 117         0x00350035,
 118         0x00350035,
 119         0x00350035,
 120         0x00350035,
 121         0x00000000,
 122         0x00000000,
 123         0x00000000,
 124         0x00000000,
 125         0x00000000,
 126         0x00000000,
 127         0x00000000,
 128         0x00000000,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000,
 133         0x40001000,
 134         0x08102040
 135 };
 136
 137 const struct ctrl_ioregs ioregs_lpddr2 = {
 138         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 139         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 140         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 141         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 142         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 143         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 144         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 145         .emif_sdram_config_ext  = 0x1,
 146 };
 147
 148 const struct emif_regs emif_regs_lpddr2 = {
 149         .sdram_config                   = 0x808012BA,
 150         .ref_ctrl                       = 0x0000040D,
 151         .sdram_tim1                     = 0xEA86B411,
 152         .sdram_tim2                     = 0x103A094A,
 153         .sdram_tim3                     = 0x0F6BA37F,
 154         .read_idle_ctrl                 = 0x00050000,
 155         .zq_config                      = 0x50074BE4,
 156         .temp_alert_config              = 0x0,
 157         .emif_rd_wr_lvl_rmp_win         = 0x0,
 158         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 159         .emif_rd_wr_lvl_ctl             = 0x0,
 160         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 161         .emif_rd_wr_exec_thresh         = 0x80000405,
 162         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 163         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 164         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 165         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 166         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 167         .emif_prio_class_serv_map       = 0x80000001,
 168         .emif_connect_id_serv_1_map     = 0x80000094,
 169         .emif_connect_id_serv_2_map     = 0x00000000,
 170         .emif_cos_config                        = 0x000FFFFF
 171 };
 172
 173 const struct ctrl_ioregs ioregs_ddr3 = {
 174         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 175         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 176         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 177         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 178         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 179         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 180         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 181         .emif_sdram_config_ext  = 0xc163,
 182 };
 183
 184 const struct emif_regs ddr3_emif_regs_400Mhz = {
 185         .sdram_config                   = 0x638413B2,
 186         .ref_ctrl                       = 0x00000C30,
 187         .sdram_tim1                     = 0xEAAAD4DB,
 188         .sdram_tim2                     = 0x266B7FDA,
 189         .sdram_tim3                     = 0x107F8678,
 190         .read_idle_ctrl                 = 0x00050000,
 191         .zq_config                      = 0x50074BE4,
 192         .temp_alert_config              = 0x0,
 193         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 194         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 195         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 196         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 197         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 198         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 199         .emif_rd_wr_lvl_rmp_win         = 0x0,
 200         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 201         .emif_rd_wr_lvl_ctl             = 0x0,
 202         .emif_rd_wr_exec_thresh         = 0x80000405,
 203         .emif_prio_class_serv_map       = 0x80000001,
 204         .emif_connect_id_serv_1_map     = 0x80000094,
 205         .emif_connect_id_serv_2_map     = 0x00000000,
 206         .emif_cos_config                = 0x000FFFFF
 207 };
 208
 209 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 210 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 211         .sdram_config                   = 0x638413B2,
 212         .ref_ctrl                       = 0x00000C30,
 213         .sdram_tim1                     = 0xEAAAD4DB,
 214         .sdram_tim2                     = 0x266B7FDA,
 215         .sdram_tim3                     = 0x107F8678,
 216         .read_idle_ctrl                 = 0x00050000,
 217         .zq_config                      = 0x50074BE4,
 218         .temp_alert_config              = 0x0,
 219         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 220         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 221         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 222         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 223         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 224         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 225         .emif_rd_wr_exec_thresh         = 0x80000405,
 226         .emif_prio_class_serv_map       = 0x80000001,
 227         .emif_connect_id_serv_1_map     = 0x80000094,
 228         .emif_connect_id_serv_2_map     = 0x00000000,
 229         .emif_cos_config                = 0x000FFFFF
 230 };
 231
 232 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 233 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 234         .sdram_config                   = 0x638413B2,
 235         .ref_ctrl                       = 0x00000C30,
 236         .sdram_tim1                     = 0xEAAAD4DB,
 237         .sdram_tim2                     = 0x266B7FDA,
 238         .sdram_tim3                     = 0x107F8678,
 239         .read_idle_ctrl                 = 0x00050000,
 240         .zq_config                      = 0x50074BE4,
 241         .temp_alert_config              = 0x0,
 242         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 243         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 244         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 245         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 246         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 247         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 248         .emif_rd_wr_exec_thresh         = 0x80000405,
 249         .emif_prio_class_serv_map       = 0x80000001,
 250         .emif_connect_id_serv_1_map     = 0x80000094,
 251         .emif_connect_id_serv_2_map     = 0x00000000,
 252         .emif_cos_config                = 0x000FFFFF
 253 };
 254
 255 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 256         .sdram_config                   = 0x638413b2,
 257         .sdram_config2                  = 0x00000000,
 258         .ref_ctrl                       = 0x00000c30,
 259         .sdram_tim1                     = 0xeaaad4db,
 260         .sdram_tim2                     = 0x266b7fda,
 261         .sdram_tim3                     = 0x107f8678,
 262         .read_idle_ctrl                 = 0x00050000,
 263         .zq_config                      = 0x50074be4,
 264         .temp_alert_config              = 0x0,
 265         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 266         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 267         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 268         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 269         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 270         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 271         .emif_rd_wr_lvl_rmp_win         = 0x0,
 272         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 273         .emif_rd_wr_lvl_ctl             = 0x00000000,
 274         .emif_rd_wr_exec_thresh         = 0x80000000,
 275         .emif_prio_class_serv_map       = 0x80000001,
 276         .emif_connect_id_serv_1_map     = 0x80000094,
 277         .emif_connect_id_serv_2_map     = 0x00000000,
 278         .emif_cos_config                = 0x000FFFFF
 279 };
 280
 281 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 282         .sdram_config                   = 0x61a11b32,
 283         .sdram_config2                  = 0x00000000,
 284         .ref_ctrl                       = 0x00000c30,
 285         .sdram_tim1                     = 0xeaaad4db,
 286         .sdram_tim2                     = 0x266b7fda,
 287         .sdram_tim3                     = 0x107f8678,
 288         .read_idle_ctrl                 = 0x00050000,
 289         .zq_config                      = 0x50074be4,
 290         .temp_alert_config              = 0x00000000,
 291         .emif_ddr_phy_ctlr_1            = 0x00008009,
 292         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 293         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 294         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 295         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 296         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 297         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 298         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 299         .emif_rd_wr_lvl_ctl             = 0x00000000,
 300         .emif_rd_wr_exec_thresh         = 0x00000405,
 301         .emif_prio_class_serv_map       = 0x00000000,
 302         .emif_connect_id_serv_1_map     = 0x00000000,
 303         .emif_connect_id_serv_2_map     = 0x00000000,
 304         .emif_cos_config                = 0x00ffffff
 305 };
 306
 307 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 308 {
 309         if (board_is_eposevm()) {
 310                 *regs = ext_phy_ctrl_const_base_lpddr2;
 311                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 312         }
 313
 314         return;
 315 }
 316
 317 /*
 318  * get_sys_clk_index : returns the index of the sys_clk read from
 319  *                      ctrl status register. This value is either
 320  *                      read from efuse or sysboot pins.
 321  */
 322 static u32 get_sys_clk_index(void)
 323 {
 324         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 325         u32 ind = readl(&ctrl->statusreg), src;
 326
 327         src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
 328         if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
 329                 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
 330                         CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
 331         else /* Value read from SYS BOOT pins */
 332                 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
 333                         CTRL_SYSBOOT_15_14_SHIFT);
 334 }
 335
 336 const struct dpll_params *get_dpll_ddr_params(void)
 337 {
 338         int ind = get_sys_clk_index();
 339
 340         if (read_eeprom() < 0)
 341                 return NULL;
 342
 343         if (board_is_eposevm())
 344                 return &epos_evm_dpll_ddr[ind];
 345         else if (board_is_evm() || board_is_sk())
 346                 return &gp_evm_dpll_ddr;
 347         else if (board_is_idk())
 348                 return &idk_dpll_ddr;
 349
 350         printf(" Board '%s' not supported\n", board_ti_get_name());
 351         return NULL;
 352 }
 353
 354
 355 /*
 356  * get_opp_offset:
 357  * Returns the index for safest OPP of the device to boot.
 358  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 359  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 360  * This data is read from dev_attribute register which is e-fused.
 361  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 362  * OPP available. Lowest OPP starts with min_off. So returning the
 363  * bit with rightmost '0'.
 364  */
 365 static int get_opp_offset(int max_off, int min_off)
 366 {
 367         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 368         int opp, offset, i;
 369
 370         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 371         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 372
 373         for (i = max_off; i >= min_off; i--) {
 374                 offset = opp & (1 << i);
 375                 if (!offset)
 376                         return i;
 377         }
 378
 379         return min_off;
 380 }
 381
 382 const struct dpll_params *get_dpll_mpu_params(void)
 383 {
 384         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 385         u32 ind = get_sys_clk_index();
 386
 387         return &dpll_mpu[ind][opp];
 388 }
 389
 390 const struct dpll_params *get_dpll_core_params(void)
 391 {
 392         int ind = get_sys_clk_index();
 393
 394         return &dpll_core[ind];
 395 }
 396
 397 const struct dpll_params *get_dpll_per_params(void)
 398 {
 399         int ind = get_sys_clk_index();
 400
 401         return &dpll_per[ind];
 402 }
 403
 404 void scale_vcores_generic(u32 m)
 405 {
 406         int mpu_vdd;
 407
 408         if (i2c_probe(TPS65218_CHIP_PM))
 409                 return;
 410
 411         switch (m) {
 412         case 1000:
 413                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 414                 break;
 415         case 800:
 416                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 417                 break;
 418         case 720:
 419                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 420                 break;
 421         case 600:
 422                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 423                 break;
 424         case 300:
 425                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 426                 break;
 427         default:
 428                 puts("Unknown MPU clock, not scaling\n");
 429                 return;
 430         }
 431
 432         /* Set DCDC1 (CORE) voltage to 1.1V */
 433         if (tps65218_voltage_update(TPS65218_DCDC1,
 434                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 435                 printf("%s failure\n", __func__);
 436                 return;
 437         }
 438
 439         /* Set DCDC2 (MPU) voltage */
 440         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 441                 printf("%s failure\n", __func__);
 442                 return;
 443         }
 444 }
 445
 446 void scale_vcores_idk(u32 m)
 447 {
 448         int mpu_vdd;
 449
 450         if (i2c_probe(TPS62362_I2C_ADDR))
 451                 return;
 452
 453         switch (m) {
 454         case 1000:
 455                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 456                 break;
 457         case 800:
 458                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 459                 break;
 460         case 720:
 461                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 462                 break;
 463         case 600:
 464                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 465                 break;
 466         case 300:
 467                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 468                 break;
 469         default:
 470                 puts("Unknown MPU clock, not scaling\n");
 471                 return;
 472         }
 473
 474         /* Set VDD_MPU voltage */
 475         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 476                 printf("%s failure\n", __func__);
 477                 return;
 478         }
 479 }
 480
 481 void gpi2c_init(void)
 482 {
 483         /* When needed to be invoked prior to BSS initialization */
 484         static bool first_time = true;
 485
 486         if (first_time) {
 487                 enable_i2c0_pin_mux();
 488                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 489                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 490                 first_time = false;
 491         }
 492 }
 493
 494 void scale_vcores(void)
 495 {
 496         const struct dpll_params *mpu_params;
 497
 498         if (read_eeprom() < 0)
 499                 puts("Could not get board ID.\n");
 500
 501         /* Ensure I2C is initialized for PMIC configuration */
 502         gpi2c_init();
 503
 504         /* Get the frequency */
 505         mpu_params = get_dpll_mpu_params();
 506
 507         if (board_is_idk())
 508                 scale_vcores_idk(mpu_params->m);
 509         else
 510                 scale_vcores_generic(mpu_params->m);
 511 }
 512
 513 void set_uart_mux_conf(void)
 514 {
 515         enable_uart0_pin_mux();
 516 }
 517
 518 void set_mux_conf_regs(void)
 519 {
 520         enable_board_pin_mux();
 521 }
 522
 523 static void enable_vtt_regulator(void)
 524 {
 525         u32 temp;
 526
 527         /* enable module */
 528         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 529
 530         /* enable output for GPIO5_7 */
 531         writel(GPIO_SETDATAOUT(7),
 532                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 533         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 534         temp = temp & ~(GPIO_OE_ENABLE(7));
 535         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 536 }
 537
 538 void sdram_init(void)
 539 {
 540         if (read_eeprom() < 0)
 541                 return;
 542         /*
 543          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 544          * GP EMV has 1GB DDR3 connected to EMIF
 545          * along with VTT regulator.
 546          */
 547         if (board_is_eposevm()) {
 548                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 549         } else if (board_is_evm_14_or_later()) {
 550                 enable_vtt_regulator();
 551                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 552                            &ddr3_emif_regs_400Mhz_production, 0);
 553         } else if (board_is_evm_12_or_later()) {
 554                 enable_vtt_regulator();
 555                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 556                            &ddr3_emif_regs_400Mhz_beta, 0);
 557         } else if (board_is_evm()) {
 558                 enable_vtt_regulator();
 559                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 560                            &ddr3_emif_regs_400Mhz, 0);
 561         } else if (board_is_sk()) {
 562                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 563                            &ddr3_sk_emif_regs_400Mhz, 0);
 564         } else if (board_is_idk()) {
 565                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 566                            &ddr3_idk_emif_regs_400Mhz, 0);
 567         }
 568 }
 569 #endif
 570
 571 /* setup board specific PMIC */
 572 int power_init_board(void)
 573 {
 574         struct pmic *p;
 575
 576         if (board_is_idk()) {
 577                 power_tps62362_init(I2C_PMIC);
 578                 p = pmic_get("TPS62362");
 579                 if (p && !pmic_probe(p))
 580                         puts("PMIC:  TPS62362\n");
 581         } else {
 582                 power_tps65218_init(I2C_PMIC);
 583                 p = pmic_get("TPS65218_PMIC");
 584                 if (p && !pmic_probe(p))
 585                         puts("PMIC:  TPS65218\n");
 586         }
 587
 588         return 0;
 589 }
 590
 591 int board_init(void)
 592 {
 593         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 594         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 595             modena_init0_bw_integer, modena_init0_watermark_0;
 596
 597         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 598         gpmc_init();
 599
 600         /* Clear all important bits for DSS errata that may need to be tweaked*/
 601         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 602                            MREQPRIO_0_SAB_INIT0_MASK;
 603
 604         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 605
 606         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 607                                            BW_LIMITER_BW_FRAC_MASK;
 608
 609         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 610                                         BW_LIMITER_BW_INT_MASK;
 611
 612         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 613                                          BW_LIMITER_BW_WATERMARK_MASK;
 614
 615         /* Setting MReq Priority of the DSS*/
 616         mreqprio_0 |= 0x77;
 617
 618         /*
 619          * Set L3 Fast Configuration Register
 620          * Limiting bandwith for ARM core to 700 MBPS
 621          */
 622         modena_init0_bw_fractional |= 0x10;
 623         modena_init0_bw_integer |= 0x3;
 624
 625         writel(mreqprio_0, &cdev->mreqprio_0);
 626         writel(mreqprio_1, &cdev->mreqprio_1);
 627
 628         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 629         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 630         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 631
 632         return 0;
 633 }
 634
 635 #ifdef CONFIG_BOARD_LATE_INIT
 636 int board_late_init(void)
 637 {
 638 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 639         set_board_info_env(NULL);
 640 #endif
 641         return 0;
 642 }
 643 #endif
 644
 645 #ifdef CONFIG_USB_DWC3
 646 static struct dwc3_device usb_otg_ss1 = {
 647         .maximum_speed = USB_SPEED_HIGH,
 648         .base = USB_OTG_SS1_BASE,
 649         .tx_fifo_resize = false,
 650         .index = 0,
 651 };
 652
 653 static struct dwc3_omap_device usb_otg_ss1_glue = {
 654         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 655         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 656         .index = 0,
 657 };
 658
 659 static struct ti_usb_phy_device usb_phy1_device = {
 660         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 661         .index = 0,
 662 };
 663
 664 static struct dwc3_device usb_otg_ss2 = {
 665         .maximum_speed = USB_SPEED_HIGH,
 666         .base = USB_OTG_SS2_BASE,
 667         .tx_fifo_resize = false,
 668         .index = 1,
 669 };
 670
 671 static struct dwc3_omap_device usb_otg_ss2_glue = {
 672         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 673         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 674         .index = 1,
 675 };
 676
 677 static struct ti_usb_phy_device usb_phy2_device = {
 678         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 679         .index = 1,
 680 };
 681
 682 int usb_gadget_handle_interrupts(int index)
 683 {
 684         u32 status;
 685
 686         status = dwc3_omap_uboot_interrupt_status(index);
 687         if (status)
 688                 dwc3_uboot_handle_interrupt(index);
 689
 690         return 0;
 691 }
 692 #endif /* CONFIG_USB_DWC3 */
 693
 694 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 695 int board_usb_init(int index, enum usb_init_type init)
 696 {
 697         enable_usb_clocks(index);
 698 #ifdef CONFIG_USB_DWC3
 699         switch (index) {
 700         case 0:
 701                 if (init == USB_INIT_DEVICE) {
 702                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 703                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 704                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 705                         ti_usb_phy_uboot_init(&usb_phy1_device);
 706                         dwc3_uboot_init(&usb_otg_ss1);
 707                 }
 708                 break;
 709         case 1:
 710                 if (init == USB_INIT_DEVICE) {
 711                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 712                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 713                         ti_usb_phy_uboot_init(&usb_phy2_device);
 714                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 715                         dwc3_uboot_init(&usb_otg_ss2);
 716                 }
 717                 break;
 718         default:
 719                 printf("Invalid Controller Index\n");
 720         }
 721 #endif
 722
 723         return 0;
 724 }
 725
 726 int board_usb_cleanup(int index, enum usb_init_type init)
 727 {
 728 #ifdef CONFIG_USB_DWC3
 729         switch (index) {
 730         case 0:
 731         case 1:
 732                 if (init == USB_INIT_DEVICE) {
 733                         ti_usb_phy_uboot_exit(index);
 734                         dwc3_uboot_exit(index);
 735                         dwc3_omap_uboot_exit(index);
 736                 }
 737                 break;
 738         default:
 739                 printf("Invalid Controller Index\n");
 740         }
 741 #endif
 742         disable_usb_clocks(index);
 743
 744         return 0;
 745 }
 746 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 747
 748 #ifdef CONFIG_DRIVER_TI_CPSW
 749
 750 static void cpsw_control(int enabled)
 751 {
 752         /* Additional controls can be added here */
 753         return;
 754 }
 755
 756 static struct cpsw_slave_data cpsw_slaves[] = {
 757         {
 758                 .slave_reg_ofs  = 0x208,
 759                 .sliver_reg_ofs = 0xd80,
 760                 .phy_addr       = 16,
 761         },
 762         {
 763                 .slave_reg_ofs  = 0x308,
 764                 .sliver_reg_ofs = 0xdc0,
 765                 .phy_addr       = 1,
 766         },
 767 };
 768
 769 static struct cpsw_platform_data cpsw_data = {
 770         .mdio_base              = CPSW_MDIO_BASE,
 771         .cpsw_base              = CPSW_BASE,
 772         .mdio_div               = 0xff,
 773         .channels               = 8,
 774         .cpdma_reg_ofs          = 0x800,
 775         .slaves                 = 1,
 776         .slave_data             = cpsw_slaves,
 777         .ale_reg_ofs            = 0xd00,
 778         .ale_entries            = 1024,
 779         .host_port_reg_ofs      = 0x108,
 780         .hw_stats_reg_ofs       = 0x900,
 781         .bd_ram_ofs             = 0x2000,
 782         .mac_control            = (1 << 5),
 783         .control                = cpsw_control,
 784         .host_port_num          = 0,
 785         .version                = CPSW_CTRL_VERSION_2,
 786 };
 787
 788 int board_eth_init(bd_t *bis)
 789 {
 790         int rv;
 791         uint8_t mac_addr[6];
 792         uint32_t mac_hi, mac_lo;
 793
 794         /* try reading mac address from efuse */
 795         mac_lo = readl(&cdev->macid0l);
 796         mac_hi = readl(&cdev->macid0h);
 797         mac_addr[0] = mac_hi & 0xFF;
 798         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 799         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 800         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 801         mac_addr[4] = mac_lo & 0xFF;
 802         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 803
 804         if (!getenv("ethaddr")) {
 805                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 806                 if (is_valid_ethaddr(mac_addr))
 807                         eth_setenv_enetaddr("ethaddr", mac_addr);
 808         }
 809
 810         mac_lo = readl(&cdev->macid1l);
 811         mac_hi = readl(&cdev->macid1h);
 812         mac_addr[0] = mac_hi & 0xFF;
 813         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 814         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 815         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 816         mac_addr[4] = mac_lo & 0xFF;
 817         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 818
 819         if (!getenv("eth1addr")) {
 820                 if (is_valid_ethaddr(mac_addr))
 821                         eth_setenv_enetaddr("eth1addr", mac_addr);
 822         }
 823
 824         if (board_is_eposevm()) {
 825                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 826                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 827                 cpsw_slaves[0].phy_addr = 16;
 828         } else if (board_is_sk()) {
 829                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 830                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 831                 cpsw_slaves[0].phy_addr = 4;
 832                 cpsw_slaves[1].phy_addr = 5;
 833         } else if (board_is_idk()) {
 834                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 835                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 836                 cpsw_slaves[0].phy_addr = 0;
 837         } else {
 838                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 839                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 840                 cpsw_slaves[0].phy_addr = 0;
 841         }
 842
 843         rv = cpsw_register(&cpsw_data);
 844         if (rv < 0)
 845                 printf("Error %d registering CPSW switch\n", rv);
 846
 847         return rv;
 848 }
 849 #endif
 850
 851 #ifdef CONFIG_SPL_LOAD_FIT
 852 int board_fit_config_name_match(const char *name)
 853 {
 854         if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 855                 return 0;
 856         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 857                 return 0;
 858         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 859                 return 0;
 860         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 861                 return 0;
 862         else
 863                 return -1;
 864 }
 865 #endif
 866
 867 #ifdef CONFIG_TI_SECURE_DEVICE
 868 void board_fit_image_post_process(void **p_image, size_t *p_size)
 869 {
 870         secure_boot_verify_image(p_image, p_size);
 871 }
 872 #endif