git.sur5r.net Git - u-boot/blob - board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <asm/errno.h>
  14 #include <spl.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/emif.h>
  21 #include "board.h"
  22 #include <power/pmic.h>
  23 #include <power/tps65218.h>
  24 #include <miiphy.h>
  25 #include <cpsw.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  30
  31 /*
  32  * Read header information from EEPROM into global structure.
  33  */
  34 static int read_eeprom(struct am43xx_board_id *header)
  35 {
  36         /* Check if baseboard eeprom is available */
  37         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  38                 printf("Could not probe the EEPROM at 0x%x\n",
  39                        CONFIG_SYS_I2C_EEPROM_ADDR);
  40                 return -ENODEV;
  41         }
  42
  43         /* read the eeprom using i2c */
  44         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  45                      sizeof(struct am43xx_board_id))) {
  46                 printf("Could not read the EEPROM\n");
  47                 return -EIO;
  48         }
  49
  50         if (header->magic != 0xEE3355AA) {
  51                 /*
  52                  * read the eeprom using i2c again,
  53                  * but use only a 1 byte address
  54                  */
  55                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  56                              sizeof(struct am43xx_board_id))) {
  57                         printf("Could not read the EEPROM at 0x%x\n",
  58                                CONFIG_SYS_I2C_EEPROM_ADDR);
  59                         return -EIO;
  60                 }
  61
  62                 if (header->magic != 0xEE3355AA) {
  63                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  64                                header->magic);
  65                         return -EINVAL;
  66                 }
  67         }
  68
  69         strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
  70         am43xx_board_name[sizeof(header->name)] = 0;
  71
  72         strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
  73         am43xx_board_rev[sizeof(header->version)] = 0;
  74
  75         return 0;
  76 }
  77
  78 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  79
  80 #define NUM_OPPS        6
  81
  82 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  83         {       /* 19.2 MHz */
  84                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  85                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  86                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  87                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  88                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  89                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  90         },
  91         {       /* 24 MHz */
  92                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  93                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  94                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  95                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  96                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  97                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  98         },
  99         {       /* 25 MHz */
 100                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
 101                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
 102                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
 103                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
 104                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
 105                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
 106         },
 107         {       /* 26 MHz */
 108                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
 109                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
 110                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
 111                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
 112                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
 113                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
 114         },
 115 };
 116
 117 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
 118                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
 119                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
 120                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
 121                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
 122 };
 123
 124 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 125                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 126                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
 127                 {32, 0, 8, -1, -1, -1, -1},     /* 25 MHz */
 128                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 129 };
 130
 131 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 132                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 133                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 134                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 135                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 136 };
 137
 138 const struct dpll_params gp_evm_dpll_ddr = {
 139                 50, 2, 1, -1, 2, -1, -1};
 140
 141 const struct ctrl_ioregs ioregs_lpddr2 = {
 142         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 143         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 144         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 145         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 146         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 147         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 148         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 149         .emif_sdram_config_ext  = 0x1,
 150 };
 151
 152 const struct emif_regs emif_regs_lpddr2 = {
 153         .sdram_config                   = 0x808012BA,
 154         .ref_ctrl                       = 0x0000040D,
 155         .sdram_tim1                     = 0xEA86B411,
 156         .sdram_tim2                     = 0x103A094A,
 157         .sdram_tim3                     = 0x0F6BA37F,
 158         .read_idle_ctrl                 = 0x00050000,
 159         .zq_config                      = 0x50074BE4,
 160         .temp_alert_config              = 0x0,
 161         .emif_rd_wr_lvl_rmp_win         = 0x0,
 162         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 163         .emif_rd_wr_lvl_ctl             = 0x0,
 164         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 165         .emif_rd_wr_exec_thresh         = 0x80000405,
 166         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 167         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 168         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 169         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 170         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 171         .emif_prio_class_serv_map       = 0x80000001,
 172         .emif_connect_id_serv_1_map     = 0x80000094,
 173         .emif_connect_id_serv_2_map     = 0x00000000,
 174         .emif_cos_config                        = 0x000FFFFF
 175 };
 176
 177 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 178         0x00500050,
 179         0x00350035,
 180         0x00350035,
 181         0x00350035,
 182         0x00350035,
 183         0x00350035,
 184         0x00000000,
 185         0x00000000,
 186         0x00000000,
 187         0x00000000,
 188         0x00000000,
 189         0x00000000,
 190         0x00000000,
 191         0x00000000,
 192         0x00000000,
 193         0x00000000,
 194         0x00000000,
 195         0x00000000,
 196         0x40001000,
 197         0x08102040
 198 };
 199
 200 const struct ctrl_ioregs ioregs_ddr3 = {
 201         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 202         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 203         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 204         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 205         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 206         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 207         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 208         .emif_sdram_config_ext  = 0xc163,
 209 };
 210
 211 const struct emif_regs ddr3_emif_regs_400Mhz = {
 212         .sdram_config                   = 0x638413B2,
 213         .ref_ctrl                       = 0x00000C30,
 214         .sdram_tim1                     = 0xEAAAD4DB,
 215         .sdram_tim2                     = 0x266B7FDA,
 216         .sdram_tim3                     = 0x107F8678,
 217         .read_idle_ctrl                 = 0x00050000,
 218         .zq_config                      = 0x50074BE4,
 219         .temp_alert_config              = 0x0,
 220         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 221         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 222         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 223         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 224         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 225         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 226         .emif_rd_wr_lvl_rmp_win         = 0x0,
 227         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 228         .emif_rd_wr_lvl_ctl             = 0x0,
 229         .emif_rd_wr_exec_thresh         = 0x80000405,
 230         .emif_prio_class_serv_map       = 0x80000001,
 231         .emif_connect_id_serv_1_map     = 0x80000094,
 232         .emif_connect_id_serv_2_map     = 0x00000000,
 233         .emif_cos_config                = 0x000FFFFF
 234 };
 235
 236 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 237 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 238         .sdram_config                   = 0x638413B2,
 239         .ref_ctrl                       = 0x00000C30,
 240         .sdram_tim1                     = 0xEAAAD4DB,
 241         .sdram_tim2                     = 0x266B7FDA,
 242         .sdram_tim3                     = 0x107F8678,
 243         .read_idle_ctrl                 = 0x00050000,
 244         .zq_config                      = 0x50074BE4,
 245         .temp_alert_config              = 0x0,
 246         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 247         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 248         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 249         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 250         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 251         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 252         .emif_rd_wr_exec_thresh         = 0x80000405,
 253         .emif_prio_class_serv_map       = 0x80000001,
 254         .emif_connect_id_serv_1_map     = 0x80000094,
 255         .emif_connect_id_serv_2_map     = 0x00000000,
 256         .emif_cos_config                = 0x000FFFFF
 257 };
 258
 259 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 260 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 261         .sdram_config                   = 0x638413B2,
 262         .ref_ctrl                       = 0x00000C30,
 263         .sdram_tim1                     = 0xEAAAD4DB,
 264         .sdram_tim2                     = 0x266B7FDA,
 265         .sdram_tim3                     = 0x107F8678,
 266         .read_idle_ctrl                 = 0x00050000,
 267         .zq_config                      = 0x50074BE4,
 268         .temp_alert_config              = 0x0,
 269         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 270         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 271         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 272         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 273         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 274         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 275         .emif_rd_wr_exec_thresh         = 0x80000405,
 276         .emif_prio_class_serv_map       = 0x80000001,
 277         .emif_connect_id_serv_1_map     = 0x80000094,
 278         .emif_connect_id_serv_2_map     = 0x00000000,
 279         .emif_cos_config                = 0x000FFFFF
 280 };
 281
 282 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 283         .sdram_config                   = 0x638413b2,
 284         .sdram_config2                  = 0x00000000,
 285         .ref_ctrl                       = 0x00000c30,
 286         .sdram_tim1                     = 0xeaaad4db,
 287         .sdram_tim2                     = 0x266b7fda,
 288         .sdram_tim3                     = 0x107f8678,
 289         .read_idle_ctrl                 = 0x00050000,
 290         .zq_config                      = 0x50074be4,
 291         .temp_alert_config              = 0x0,
 292         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 293         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 294         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 295         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 296         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 297         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 298         .emif_rd_wr_lvl_rmp_win         = 0x0,
 299         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 300         .emif_rd_wr_lvl_ctl             = 0x00000000,
 301         .emif_rd_wr_exec_thresh         = 0x80000000,
 302         .emif_prio_class_serv_map       = 0x80000001,
 303         .emif_connect_id_serv_1_map     = 0x80000094,
 304         .emif_connect_id_serv_2_map     = 0x00000000,
 305         .emif_cos_config                = 0x000FFFFF
 306 };
 307
 308 const u32 ext_phy_ctrl_const_base_ddr3[] = {
 309         0x00400040,
 310         0x00350035,
 311         0x00350035,
 312         0x00350035,
 313         0x00350035,
 314         0x00350035,
 315         0x00000000,
 316         0x00000000,
 317         0x00000000,
 318         0x00000000,
 319         0x00000000,
 320         0x00340034,
 321         0x00340034,
 322         0x00340034,
 323         0x00340034,
 324         0x00340034,
 325         0x0,
 326         0x0,
 327         0x40000000,
 328         0x08102040
 329 };
 330
 331 const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
 332         0x00000000,
 333         0x00000045,
 334         0x00000046,
 335         0x00000048,
 336         0x00000047,
 337         0x00000000,
 338         0x0000004C,
 339         0x00000070,
 340         0x00000085,
 341         0x000000A3,
 342         0x00000000,
 343         0x0000000C,
 344         0x00000030,
 345         0x00000045,
 346         0x00000063,
 347         0x00000000,
 348         0x0,
 349         0x0,
 350         0x40000000,
 351         0x08102040
 352 };
 353
 354 const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
 355         0x00000000,
 356         0x00000044,
 357         0x00000044,
 358         0x00000046,
 359         0x00000046,
 360         0x00000000,
 361         0x00000059,
 362         0x00000077,
 363         0x00000093,
 364         0x000000A8,
 365         0x00000000,
 366         0x00000019,
 367         0x00000037,
 368         0x00000053,
 369         0x00000068,
 370         0x00000000,
 371         0x0,
 372         0x0,
 373         0x40000000,
 374         0x08102040
 375 };
 376
 377 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
 378         /* first 5 are taken care by emif_regs */
 379         0x00700070,
 380
 381         0x00350035,
 382         0x00350035,
 383         0x00350035,
 384         0x00350035,
 385         0x00350035,
 386
 387         0x00000000,
 388         0x00000000,
 389         0x00000000,
 390         0x00000000,
 391         0x00000000,
 392
 393         0x00150015,
 394         0x00150015,
 395         0x00150015,
 396         0x00150015,
 397         0x00150015,
 398
 399         0x00800080,
 400         0x00800080,
 401
 402         0x40000000,
 403
 404         0x08102040,
 405
 406         0x00000000,
 407         0x00000000,
 408         0x00000000,
 409         0x00000000,
 410         0x00000000,
 411         0x00000000,
 412         0x00000000,
 413         0x00000000,
 414         0x00000000,
 415         0x00000000,
 416         0x00000000,
 417 };
 418
 419 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 420 {
 421         if (board_is_eposevm()) {
 422                 *regs = ext_phy_ctrl_const_base_lpddr2;
 423                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 424         } else if (board_is_evm_14_or_later()) {
 425                 *regs = ext_phy_ctrl_const_base_ddr3_production;
 426                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
 427         } else if (board_is_evm_12_or_later()) {
 428                 *regs = ext_phy_ctrl_const_base_ddr3_beta;
 429                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
 430         } else if (board_is_gpevm()) {
 431                 *regs = ext_phy_ctrl_const_base_ddr3;
 432                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
 433         } else if (board_is_sk()) {
 434                 *regs = ext_phy_ctrl_const_base_ddr3_sk;
 435                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
 436         }
 437
 438         return;
 439 }
 440
 441 /*
 442  * get_sys_clk_index : returns the index of the sys_clk read from
 443  *                      ctrl status register. This value is either
 444  *                      read from efuse or sysboot pins.
 445  */
 446 static u32 get_sys_clk_index(void)
 447 {
 448         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 449         u32 ind = readl(&ctrl->statusreg), src;
 450
 451         src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
 452         if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
 453                 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
 454                         CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
 455         else /* Value read from SYS BOOT pins */
 456                 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
 457                         CTRL_SYSBOOT_15_14_SHIFT);
 458 }
 459
 460 const struct dpll_params *get_dpll_ddr_params(void)
 461 {
 462         int ind = get_sys_clk_index();
 463
 464         if (board_is_eposevm())
 465                 return &epos_evm_dpll_ddr[ind];
 466         else if (board_is_gpevm() || board_is_sk())
 467                 return &gp_evm_dpll_ddr;
 468
 469         printf(" Board '%s' not supported\n", am43xx_board_name);
 470         return NULL;
 471 }
 472
 473
 474 /*
 475  * get_opp_offset:
 476  * Returns the index for safest OPP of the device to boot.
 477  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 478  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 479  * This data is read from dev_attribute register which is e-fused.
 480  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 481  * OPP available. Lowest OPP starts with min_off. So returning the
 482  * bit with rightmost '0'.
 483  */
 484 static int get_opp_offset(int max_off, int min_off)
 485 {
 486         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 487         int opp, offset, i;
 488
 489         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 490         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 491
 492         for (i = max_off; i >= min_off; i--) {
 493                 offset = opp & (1 << i);
 494                 if (!offset)
 495                         return i;
 496         }
 497
 498         return min_off;
 499 }
 500
 501 const struct dpll_params *get_dpll_mpu_params(void)
 502 {
 503         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 504         u32 ind = get_sys_clk_index();
 505
 506         return &dpll_mpu[ind][opp];
 507 }
 508
 509 const struct dpll_params *get_dpll_core_params(void)
 510 {
 511         int ind = get_sys_clk_index();
 512
 513         return &dpll_core[ind];
 514 }
 515
 516 const struct dpll_params *get_dpll_per_params(void)
 517 {
 518         int ind = get_sys_clk_index();
 519
 520         return &dpll_per[ind];
 521 }
 522
 523 void scale_vcores(void)
 524 {
 525         const struct dpll_params *mpu_params;
 526         int mpu_vdd;
 527         struct am43xx_board_id header;
 528
 529         enable_i2c0_pin_mux();
 530         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 531         if (read_eeprom(&header) < 0)
 532                 puts("Could not get board ID.\n");
 533
 534         /* Get the frequency */
 535         mpu_params = get_dpll_mpu_params();
 536
 537         if (i2c_probe(TPS65218_CHIP_PM))
 538                 return;
 539
 540         if (mpu_params->m == 1000) {
 541                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 542         } else if (mpu_params->m == 600) {
 543                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 544         } else {
 545                 puts("Unknown MPU clock, not scaling\n");
 546                 return;
 547         }
 548
 549         /* Set DCDC1 (CORE) voltage to 1.1V */
 550         if (tps65218_voltage_update(TPS65218_DCDC1,
 551                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 552                 puts("tps65218_voltage_update failure\n");
 553                 return;
 554         }
 555
 556         /* Set DCDC2 (MPU) voltage */
 557         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 558                 puts("tps65218_voltage_update failure\n");
 559                 return;
 560         }
 561 }
 562
 563 void set_uart_mux_conf(void)
 564 {
 565         enable_uart0_pin_mux();
 566 }
 567
 568 void set_mux_conf_regs(void)
 569 {
 570         enable_board_pin_mux();
 571 }
 572
 573 static void enable_vtt_regulator(void)
 574 {
 575         u32 temp;
 576
 577         /* enable module */
 578         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 579
 580         /* enable output for GPIO5_7 */
 581         writel(GPIO_SETDATAOUT(7),
 582                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 583         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 584         temp = temp & ~(GPIO_OE_ENABLE(7));
 585         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 586 }
 587
 588 void sdram_init(void)
 589 {
 590         /*
 591          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 592          * GP EMV has 1GB DDR3 connected to EMIF
 593          * along with VTT regulator.
 594          */
 595         if (board_is_eposevm()) {
 596                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 597         } else if (board_is_evm_14_or_later()) {
 598                 enable_vtt_regulator();
 599                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 600                            &ddr3_emif_regs_400Mhz_production, 0);
 601         } else if (board_is_evm_12_or_later()) {
 602                 enable_vtt_regulator();
 603                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 604                            &ddr3_emif_regs_400Mhz_beta, 0);
 605         } else if (board_is_gpevm()) {
 606                 enable_vtt_regulator();
 607                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 608                            &ddr3_emif_regs_400Mhz, 0);
 609         } else if (board_is_sk()) {
 610                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 611                            &ddr3_sk_emif_regs_400Mhz, 0);
 612         }
 613 }
 614 #endif
 615
 616 /* setup board specific PMIC */
 617 int power_init_board(void)
 618 {
 619         struct pmic *p;
 620
 621         power_tps65218_init(I2C_PMIC);
 622         p = pmic_get("TPS65218_PMIC");
 623         if (p && !pmic_probe(p))
 624                 puts("PMIC:  TPS65218\n");
 625
 626         return 0;
 627 }
 628
 629 int board_init(void)
 630 {
 631         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 632         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 633             modena_init0_bw_integer, modena_init0_watermark_0;
 634
 635         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 636         gpmc_init();
 637
 638         /* Clear all important bits for DSS errata that may need to be tweaked*/
 639         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 640                            MREQPRIO_0_SAB_INIT0_MASK;
 641
 642         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 643
 644         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 645                                            BW_LIMITER_BW_FRAC_MASK;
 646
 647         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 648                                         BW_LIMITER_BW_INT_MASK;
 649
 650         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 651                                          BW_LIMITER_BW_WATERMARK_MASK;
 652
 653         /* Setting MReq Priority of the DSS*/
 654         mreqprio_0 |= 0x77;
 655
 656         /*
 657          * Set L3 Fast Configuration Register
 658          * Limiting bandwith for ARM core to 700 MBPS
 659          */
 660         modena_init0_bw_fractional |= 0x10;
 661         modena_init0_bw_integer |= 0x3;
 662
 663         writel(mreqprio_0, &cdev->mreqprio_0);
 664         writel(mreqprio_1, &cdev->mreqprio_1);
 665
 666         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 667         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 668         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 669
 670         return 0;
 671 }
 672
 673 #ifdef CONFIG_BOARD_LATE_INIT
 674 int board_late_init(void)
 675 {
 676 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 677         char safe_string[HDR_NAME_LEN + 1];
 678         struct am43xx_board_id header;
 679
 680         if (read_eeprom(&header) < 0)
 681                 puts("Could not get board ID.\n");
 682
 683         /* Now set variables based on the header. */
 684         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 685         safe_string[sizeof(header.name)] = 0;
 686         setenv("board_name", safe_string);
 687
 688         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 689         safe_string[sizeof(header.version)] = 0;
 690         setenv("board_rev", safe_string);
 691 #endif
 692         return 0;
 693 }
 694 #endif
 695
 696 #ifdef CONFIG_DRIVER_TI_CPSW
 697
 698 static void cpsw_control(int enabled)
 699 {
 700         /* Additional controls can be added here */
 701         return;
 702 }
 703
 704 static struct cpsw_slave_data cpsw_slaves[] = {
 705         {
 706                 .slave_reg_ofs  = 0x208,
 707                 .sliver_reg_ofs = 0xd80,
 708                 .phy_addr       = 16,
 709         },
 710         {
 711                 .slave_reg_ofs  = 0x308,
 712                 .sliver_reg_ofs = 0xdc0,
 713                 .phy_addr       = 1,
 714         },
 715 };
 716
 717 static struct cpsw_platform_data cpsw_data = {
 718         .mdio_base              = CPSW_MDIO_BASE,
 719         .cpsw_base              = CPSW_BASE,
 720         .mdio_div               = 0xff,
 721         .channels               = 8,
 722         .cpdma_reg_ofs          = 0x800,
 723         .slaves                 = 1,
 724         .slave_data             = cpsw_slaves,
 725         .ale_reg_ofs            = 0xd00,
 726         .ale_entries            = 1024,
 727         .host_port_reg_ofs      = 0x108,
 728         .hw_stats_reg_ofs       = 0x900,
 729         .bd_ram_ofs             = 0x2000,
 730         .mac_control            = (1 << 5),
 731         .control                = cpsw_control,
 732         .host_port_num          = 0,
 733         .version                = CPSW_CTRL_VERSION_2,
 734 };
 735
 736 int board_eth_init(bd_t *bis)
 737 {
 738         int rv;
 739         uint8_t mac_addr[6];
 740         uint32_t mac_hi, mac_lo;
 741
 742         /* try reading mac address from efuse */
 743         mac_lo = readl(&cdev->macid0l);
 744         mac_hi = readl(&cdev->macid0h);
 745         mac_addr[0] = mac_hi & 0xFF;
 746         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 747         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 748         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 749         mac_addr[4] = mac_lo & 0xFF;
 750         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 751
 752         if (!getenv("ethaddr")) {
 753                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 754                 if (is_valid_ether_addr(mac_addr))
 755                         eth_setenv_enetaddr("ethaddr", mac_addr);
 756         }
 757
 758         mac_lo = readl(&cdev->macid1l);
 759         mac_hi = readl(&cdev->macid1h);
 760         mac_addr[0] = mac_hi & 0xFF;
 761         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 762         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 763         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 764         mac_addr[4] = mac_lo & 0xFF;
 765         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 766
 767         if (!getenv("eth1addr")) {
 768                 if (is_valid_ether_addr(mac_addr))
 769                         eth_setenv_enetaddr("eth1addr", mac_addr);
 770         }
 771
 772         if (board_is_eposevm()) {
 773                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 774                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 775                 cpsw_slaves[0].phy_addr = 16;
 776         } else if (board_is_sk()) {
 777                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 778                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 779                 cpsw_slaves[0].phy_addr = 4;
 780                 cpsw_slaves[1].phy_addr = 5;
 781         } else {
 782                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 783                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 784                 cpsw_slaves[0].phy_addr = 0;
 785         }
 786
 787         rv = cpsw_register(&cpsw_data);
 788         if (rv < 0)
 789                 printf("Error %d registering CPSW switch\n", rv);
 790
 791         return rv;
 792 }
 793 #endif