git.sur5r.net Git - u-boot/blob - board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <asm/errno.h>
  14 #include <spl.h>
  15 #include <usb.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/mux.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/emif.h>
  22 #include "../common/board_detect.h"
  23 #include "board.h"
  24 #include <power/pmic.h>
  25 #include <power/tps65218.h>
  26 #include <power/tps62362.h>
  27 #include <miiphy.h>
  28 #include <cpsw.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  37
  38 /*
  39  * Read header information from EEPROM into global structure.
  40  */
  41 static inline int __maybe_unused read_eeprom(void)
  42 {
  43         return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
  44 }
  45
  46 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  47
  48 #define NUM_OPPS        6
  49
  50 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  51         {       /* 19.2 MHz */
  52                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  53                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  54                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  55                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  56                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  57                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  58         },
  59         {       /* 24 MHz */
  60                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  61                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  62                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  63                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  64                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  65                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  66         },
  67         {       /* 25 MHz */
  68                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  69                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  70                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  71                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  72                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  73                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  74         },
  75         {       /* 26 MHz */
  76                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  77                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  78                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  79                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  80                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  81                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  82         },
  83 };
  84
  85 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  86                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  87                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  88                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  89                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
  90 };
  91
  92 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  93                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
  94                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
  95                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
  96                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
  97 };
  98
  99 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 100                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 101                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 102                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 103                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 104 };
 105
 106 const struct dpll_params gp_evm_dpll_ddr = {
 107                 50, 2, 1, -1, 2, -1, -1};
 108
 109 static const struct dpll_params idk_dpll_ddr = {
 110         400, 23, 1, -1, 2, -1, -1
 111 };
 112
 113 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 114         0x00500050,
 115         0x00350035,
 116         0x00350035,
 117         0x00350035,
 118         0x00350035,
 119         0x00350035,
 120         0x00000000,
 121         0x00000000,
 122         0x00000000,
 123         0x00000000,
 124         0x00000000,
 125         0x00000000,
 126         0x00000000,
 127         0x00000000,
 128         0x00000000,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x40001000,
 133         0x08102040
 134 };
 135
 136 const struct ctrl_ioregs ioregs_lpddr2 = {
 137         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 138         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 139         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 140         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 141         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 142         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 143         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 144         .emif_sdram_config_ext  = 0x1,
 145 };
 146
 147 const struct emif_regs emif_regs_lpddr2 = {
 148         .sdram_config                   = 0x808012BA,
 149         .ref_ctrl                       = 0x0000040D,
 150         .sdram_tim1                     = 0xEA86B411,
 151         .sdram_tim2                     = 0x103A094A,
 152         .sdram_tim3                     = 0x0F6BA37F,
 153         .read_idle_ctrl                 = 0x00050000,
 154         .zq_config                      = 0x50074BE4,
 155         .temp_alert_config              = 0x0,
 156         .emif_rd_wr_lvl_rmp_win         = 0x0,
 157         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 158         .emif_rd_wr_lvl_ctl             = 0x0,
 159         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 160         .emif_rd_wr_exec_thresh         = 0x80000405,
 161         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 162         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 163         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 164         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 165         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 166         .emif_prio_class_serv_map       = 0x80000001,
 167         .emif_connect_id_serv_1_map     = 0x80000094,
 168         .emif_connect_id_serv_2_map     = 0x00000000,
 169         .emif_cos_config                        = 0x000FFFFF
 170 };
 171
 172 const struct ctrl_ioregs ioregs_ddr3 = {
 173         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 174         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 175         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 176         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 177         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 178         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 179         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 180         .emif_sdram_config_ext  = 0xc163,
 181 };
 182
 183 const struct emif_regs ddr3_emif_regs_400Mhz = {
 184         .sdram_config                   = 0x638413B2,
 185         .ref_ctrl                       = 0x00000C30,
 186         .sdram_tim1                     = 0xEAAAD4DB,
 187         .sdram_tim2                     = 0x266B7FDA,
 188         .sdram_tim3                     = 0x107F8678,
 189         .read_idle_ctrl                 = 0x00050000,
 190         .zq_config                      = 0x50074BE4,
 191         .temp_alert_config              = 0x0,
 192         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 193         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 194         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 195         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 196         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 197         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 198         .emif_rd_wr_lvl_rmp_win         = 0x0,
 199         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 200         .emif_rd_wr_lvl_ctl             = 0x0,
 201         .emif_rd_wr_exec_thresh         = 0x80000405,
 202         .emif_prio_class_serv_map       = 0x80000001,
 203         .emif_connect_id_serv_1_map     = 0x80000094,
 204         .emif_connect_id_serv_2_map     = 0x00000000,
 205         .emif_cos_config                = 0x000FFFFF
 206 };
 207
 208 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 209 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 210         .sdram_config                   = 0x638413B2,
 211         .ref_ctrl                       = 0x00000C30,
 212         .sdram_tim1                     = 0xEAAAD4DB,
 213         .sdram_tim2                     = 0x266B7FDA,
 214         .sdram_tim3                     = 0x107F8678,
 215         .read_idle_ctrl                 = 0x00050000,
 216         .zq_config                      = 0x50074BE4,
 217         .temp_alert_config              = 0x0,
 218         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 219         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 220         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 221         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 222         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 223         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 224         .emif_rd_wr_exec_thresh         = 0x80000405,
 225         .emif_prio_class_serv_map       = 0x80000001,
 226         .emif_connect_id_serv_1_map     = 0x80000094,
 227         .emif_connect_id_serv_2_map     = 0x00000000,
 228         .emif_cos_config                = 0x000FFFFF
 229 };
 230
 231 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 232 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 233         .sdram_config                   = 0x638413B2,
 234         .ref_ctrl                       = 0x00000C30,
 235         .sdram_tim1                     = 0xEAAAD4DB,
 236         .sdram_tim2                     = 0x266B7FDA,
 237         .sdram_tim3                     = 0x107F8678,
 238         .read_idle_ctrl                 = 0x00050000,
 239         .zq_config                      = 0x50074BE4,
 240         .temp_alert_config              = 0x0,
 241         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 242         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 243         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 244         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 245         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 246         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 247         .emif_rd_wr_exec_thresh         = 0x80000405,
 248         .emif_prio_class_serv_map       = 0x80000001,
 249         .emif_connect_id_serv_1_map     = 0x80000094,
 250         .emif_connect_id_serv_2_map     = 0x00000000,
 251         .emif_cos_config                = 0x000FFFFF
 252 };
 253
 254 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 255         .sdram_config                   = 0x638413b2,
 256         .sdram_config2                  = 0x00000000,
 257         .ref_ctrl                       = 0x00000c30,
 258         .sdram_tim1                     = 0xeaaad4db,
 259         .sdram_tim2                     = 0x266b7fda,
 260         .sdram_tim3                     = 0x107f8678,
 261         .read_idle_ctrl                 = 0x00050000,
 262         .zq_config                      = 0x50074be4,
 263         .temp_alert_config              = 0x0,
 264         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 265         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 266         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 267         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 268         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 269         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 270         .emif_rd_wr_lvl_rmp_win         = 0x0,
 271         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 272         .emif_rd_wr_lvl_ctl             = 0x00000000,
 273         .emif_rd_wr_exec_thresh         = 0x80000000,
 274         .emif_prio_class_serv_map       = 0x80000001,
 275         .emif_connect_id_serv_1_map     = 0x80000094,
 276         .emif_connect_id_serv_2_map     = 0x00000000,
 277         .emif_cos_config                = 0x000FFFFF
 278 };
 279
 280 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 281         .sdram_config                   = 0x61a11b32,
 282         .sdram_config2                  = 0x00000000,
 283         .ref_ctrl                       = 0x00000c30,
 284         .sdram_tim1                     = 0xeaaad4db,
 285         .sdram_tim2                     = 0x266b7fda,
 286         .sdram_tim3                     = 0x107f8678,
 287         .read_idle_ctrl                 = 0x00050000,
 288         .zq_config                      = 0x50074be4,
 289         .temp_alert_config              = 0x00000000,
 290         .emif_ddr_phy_ctlr_1            = 0x00008009,
 291         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 292         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 293         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 294         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 295         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 296         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 297         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 298         .emif_rd_wr_lvl_ctl             = 0x00000000,
 299         .emif_rd_wr_exec_thresh         = 0x00000405,
 300         .emif_prio_class_serv_map       = 0x00000000,
 301         .emif_connect_id_serv_1_map     = 0x00000000,
 302         .emif_connect_id_serv_2_map     = 0x00000000,
 303         .emif_cos_config                = 0x00ffffff
 304 };
 305
 306 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 307 {
 308         if (board_is_eposevm()) {
 309                 *regs = ext_phy_ctrl_const_base_lpddr2;
 310                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 311         }
 312
 313         return;
 314 }
 315
 316 /*
 317  * get_sys_clk_index : returns the index of the sys_clk read from
 318  *                      ctrl status register. This value is either
 319  *                      read from efuse or sysboot pins.
 320  */
 321 static u32 get_sys_clk_index(void)
 322 {
 323         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 324         u32 ind = readl(&ctrl->statusreg), src;
 325
 326         src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
 327         if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
 328                 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
 329                         CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
 330         else /* Value read from SYS BOOT pins */
 331                 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
 332                         CTRL_SYSBOOT_15_14_SHIFT);
 333 }
 334
 335 const struct dpll_params *get_dpll_ddr_params(void)
 336 {
 337         int ind = get_sys_clk_index();
 338
 339         if (read_eeprom() < 0)
 340                 return NULL;
 341
 342         if (board_is_eposevm())
 343                 return &epos_evm_dpll_ddr[ind];
 344         else if (board_is_gpevm() || board_is_sk())
 345                 return &gp_evm_dpll_ddr;
 346         else if (board_is_idk())
 347                 return &idk_dpll_ddr;
 348
 349         printf(" Board '%s' not supported\n", board_ti_get_name());
 350         return NULL;
 351 }
 352
 353
 354 /*
 355  * get_opp_offset:
 356  * Returns the index for safest OPP of the device to boot.
 357  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 358  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 359  * This data is read from dev_attribute register which is e-fused.
 360  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 361  * OPP available. Lowest OPP starts with min_off. So returning the
 362  * bit with rightmost '0'.
 363  */
 364 static int get_opp_offset(int max_off, int min_off)
 365 {
 366         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 367         int opp, offset, i;
 368
 369         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 370         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 371
 372         for (i = max_off; i >= min_off; i--) {
 373                 offset = opp & (1 << i);
 374                 if (!offset)
 375                         return i;
 376         }
 377
 378         return min_off;
 379 }
 380
 381 const struct dpll_params *get_dpll_mpu_params(void)
 382 {
 383         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 384         u32 ind = get_sys_clk_index();
 385
 386         return &dpll_mpu[ind][opp];
 387 }
 388
 389 const struct dpll_params *get_dpll_core_params(void)
 390 {
 391         int ind = get_sys_clk_index();
 392
 393         return &dpll_core[ind];
 394 }
 395
 396 const struct dpll_params *get_dpll_per_params(void)
 397 {
 398         int ind = get_sys_clk_index();
 399
 400         return &dpll_per[ind];
 401 }
 402
 403 void scale_vcores_generic(u32 m)
 404 {
 405         int mpu_vdd;
 406
 407         if (i2c_probe(TPS65218_CHIP_PM))
 408                 return;
 409
 410         switch (m) {
 411         case 1000:
 412                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 413                 break;
 414         case 800:
 415                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 416                 break;
 417         case 720:
 418                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 419                 break;
 420         case 600:
 421                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 422                 break;
 423         case 300:
 424                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 425                 break;
 426         default:
 427                 puts("Unknown MPU clock, not scaling\n");
 428                 return;
 429         }
 430
 431         /* Set DCDC1 (CORE) voltage to 1.1V */
 432         if (tps65218_voltage_update(TPS65218_DCDC1,
 433                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 434                 printf("%s failure\n", __func__);
 435                 return;
 436         }
 437
 438         /* Set DCDC2 (MPU) voltage */
 439         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 440                 printf("%s failure\n", __func__);
 441                 return;
 442         }
 443 }
 444
 445 void scale_vcores_idk(u32 m)
 446 {
 447         int mpu_vdd;
 448
 449         if (i2c_probe(TPS62362_I2C_ADDR))
 450                 return;
 451
 452         switch (m) {
 453         case 1000:
 454                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 455                 break;
 456         case 800:
 457                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 458                 break;
 459         case 720:
 460                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 461                 break;
 462         case 600:
 463                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 464                 break;
 465         case 300:
 466                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 467                 break;
 468         default:
 469                 puts("Unknown MPU clock, not scaling\n");
 470                 return;
 471         }
 472
 473         /* Set VDD_MPU voltage */
 474         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 475                 printf("%s failure\n", __func__);
 476                 return;
 477         }
 478 }
 479
 480 void gpi2c_init(void)
 481 {
 482         /* When needed to be invoked prior to BSS initialization */
 483         static bool first_time = true;
 484
 485         if (first_time) {
 486                 enable_i2c0_pin_mux();
 487                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 488                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 489                 first_time = false;
 490         }
 491 }
 492
 493 void scale_vcores(void)
 494 {
 495         const struct dpll_params *mpu_params;
 496
 497         if (read_eeprom() < 0)
 498                 puts("Could not get board ID.\n");
 499
 500         /* Ensure I2C is initialized for PMIC configuration */
 501         gpi2c_init();
 502
 503         /* Get the frequency */
 504         mpu_params = get_dpll_mpu_params();
 505
 506         if (board_is_idk())
 507                 scale_vcores_idk(mpu_params->m);
 508         else
 509                 scale_vcores_generic(mpu_params->m);
 510 }
 511
 512 void set_uart_mux_conf(void)
 513 {
 514         enable_uart0_pin_mux();
 515 }
 516
 517 void set_mux_conf_regs(void)
 518 {
 519         enable_board_pin_mux();
 520 }
 521
 522 static void enable_vtt_regulator(void)
 523 {
 524         u32 temp;
 525
 526         /* enable module */
 527         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 528
 529         /* enable output for GPIO5_7 */
 530         writel(GPIO_SETDATAOUT(7),
 531                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 532         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 533         temp = temp & ~(GPIO_OE_ENABLE(7));
 534         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 535 }
 536
 537 void sdram_init(void)
 538 {
 539         if (read_eeprom() < 0)
 540                 return;
 541         /*
 542          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 543          * GP EMV has 1GB DDR3 connected to EMIF
 544          * along with VTT regulator.
 545          */
 546         if (board_is_eposevm()) {
 547                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 548         } else if (board_is_evm_14_or_later()) {
 549                 enable_vtt_regulator();
 550                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 551                            &ddr3_emif_regs_400Mhz_production, 0);
 552         } else if (board_is_evm_12_or_later()) {
 553                 enable_vtt_regulator();
 554                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 555                            &ddr3_emif_regs_400Mhz_beta, 0);
 556         } else if (board_is_gpevm()) {
 557                 enable_vtt_regulator();
 558                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 559                            &ddr3_emif_regs_400Mhz, 0);
 560         } else if (board_is_sk()) {
 561                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 562                            &ddr3_sk_emif_regs_400Mhz, 0);
 563         } else if (board_is_idk()) {
 564                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 565                            &ddr3_idk_emif_regs_400Mhz, 0);
 566         }
 567 }
 568 #endif
 569
 570 /* setup board specific PMIC */
 571 int power_init_board(void)
 572 {
 573         struct pmic *p;
 574
 575         if (board_is_idk()) {
 576                 power_tps62362_init(I2C_PMIC);
 577                 p = pmic_get("TPS62362");
 578                 if (p && !pmic_probe(p))
 579                         puts("PMIC:  TPS62362\n");
 580         } else {
 581                 power_tps65218_init(I2C_PMIC);
 582                 p = pmic_get("TPS65218_PMIC");
 583                 if (p && !pmic_probe(p))
 584                         puts("PMIC:  TPS65218\n");
 585         }
 586
 587         return 0;
 588 }
 589
 590 int board_init(void)
 591 {
 592         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 593         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 594             modena_init0_bw_integer, modena_init0_watermark_0;
 595
 596         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 597         gpmc_init();
 598
 599         /* Clear all important bits for DSS errata that may need to be tweaked*/
 600         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 601                            MREQPRIO_0_SAB_INIT0_MASK;
 602
 603         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 604
 605         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 606                                            BW_LIMITER_BW_FRAC_MASK;
 607
 608         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 609                                         BW_LIMITER_BW_INT_MASK;
 610
 611         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 612                                          BW_LIMITER_BW_WATERMARK_MASK;
 613
 614         /* Setting MReq Priority of the DSS*/
 615         mreqprio_0 |= 0x77;
 616
 617         /*
 618          * Set L3 Fast Configuration Register
 619          * Limiting bandwith for ARM core to 700 MBPS
 620          */
 621         modena_init0_bw_fractional |= 0x10;
 622         modena_init0_bw_integer |= 0x3;
 623
 624         writel(mreqprio_0, &cdev->mreqprio_0);
 625         writel(mreqprio_1, &cdev->mreqprio_1);
 626
 627         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 628         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 629         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 630
 631         return 0;
 632 }
 633
 634 #ifdef CONFIG_BOARD_LATE_INIT
 635 int board_late_init(void)
 636 {
 637 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 638         set_board_info_env(NULL);
 639 #endif
 640         return 0;
 641 }
 642 #endif
 643
 644 #ifdef CONFIG_USB_DWC3
 645 static struct dwc3_device usb_otg_ss1 = {
 646         .maximum_speed = USB_SPEED_HIGH,
 647         .base = USB_OTG_SS1_BASE,
 648         .tx_fifo_resize = false,
 649         .index = 0,
 650 };
 651
 652 static struct dwc3_omap_device usb_otg_ss1_glue = {
 653         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 654         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 655         .index = 0,
 656 };
 657
 658 static struct ti_usb_phy_device usb_phy1_device = {
 659         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 660         .index = 0,
 661 };
 662
 663 static struct dwc3_device usb_otg_ss2 = {
 664         .maximum_speed = USB_SPEED_HIGH,
 665         .base = USB_OTG_SS2_BASE,
 666         .tx_fifo_resize = false,
 667         .index = 1,
 668 };
 669
 670 static struct dwc3_omap_device usb_otg_ss2_glue = {
 671         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 672         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 673         .index = 1,
 674 };
 675
 676 static struct ti_usb_phy_device usb_phy2_device = {
 677         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 678         .index = 1,
 679 };
 680
 681 int board_usb_init(int index, enum usb_init_type init)
 682 {
 683         enable_usb_clocks(index);
 684         switch (index) {
 685         case 0:
 686                 if (init == USB_INIT_DEVICE) {
 687                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 688                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 689                 } else {
 690                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 691                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 692                 }
 693
 694                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 695                 ti_usb_phy_uboot_init(&usb_phy1_device);
 696                 dwc3_uboot_init(&usb_otg_ss1);
 697                 break;
 698         case 1:
 699                 if (init == USB_INIT_DEVICE) {
 700                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 701                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 702                 } else {
 703                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 704                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 705                 }
 706
 707                 ti_usb_phy_uboot_init(&usb_phy2_device);
 708                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 709                 dwc3_uboot_init(&usb_otg_ss2);
 710                 break;
 711         default:
 712                 printf("Invalid Controller Index\n");
 713         }
 714
 715         return 0;
 716 }
 717
 718 int board_usb_cleanup(int index, enum usb_init_type init)
 719 {
 720         switch (index) {
 721         case 0:
 722         case 1:
 723                 ti_usb_phy_uboot_exit(index);
 724                 dwc3_uboot_exit(index);
 725                 dwc3_omap_uboot_exit(index);
 726                 break;
 727         default:
 728                 printf("Invalid Controller Index\n");
 729         }
 730         disable_usb_clocks(index);
 731
 732         return 0;
 733 }
 734
 735 int usb_gadget_handle_interrupts(int index)
 736 {
 737         u32 status;
 738
 739         status = dwc3_omap_uboot_interrupt_status(index);
 740         if (status)
 741                 dwc3_uboot_handle_interrupt(index);
 742
 743         return 0;
 744 }
 745 #endif
 746
 747 #ifdef CONFIG_DRIVER_TI_CPSW
 748
 749 static void cpsw_control(int enabled)
 750 {
 751         /* Additional controls can be added here */
 752         return;
 753 }
 754
 755 static struct cpsw_slave_data cpsw_slaves[] = {
 756         {
 757                 .slave_reg_ofs  = 0x208,
 758                 .sliver_reg_ofs = 0xd80,
 759                 .phy_addr       = 16,
 760         },
 761         {
 762                 .slave_reg_ofs  = 0x308,
 763                 .sliver_reg_ofs = 0xdc0,
 764                 .phy_addr       = 1,
 765         },
 766 };
 767
 768 static struct cpsw_platform_data cpsw_data = {
 769         .mdio_base              = CPSW_MDIO_BASE,
 770         .cpsw_base              = CPSW_BASE,
 771         .mdio_div               = 0xff,
 772         .channels               = 8,
 773         .cpdma_reg_ofs          = 0x800,
 774         .slaves                 = 1,
 775         .slave_data             = cpsw_slaves,
 776         .ale_reg_ofs            = 0xd00,
 777         .ale_entries            = 1024,
 778         .host_port_reg_ofs      = 0x108,
 779         .hw_stats_reg_ofs       = 0x900,
 780         .bd_ram_ofs             = 0x2000,
 781         .mac_control            = (1 << 5),
 782         .control                = cpsw_control,
 783         .host_port_num          = 0,
 784         .version                = CPSW_CTRL_VERSION_2,
 785 };
 786
 787 int board_eth_init(bd_t *bis)
 788 {
 789         int rv;
 790         uint8_t mac_addr[6];
 791         uint32_t mac_hi, mac_lo;
 792
 793         /* try reading mac address from efuse */
 794         mac_lo = readl(&cdev->macid0l);
 795         mac_hi = readl(&cdev->macid0h);
 796         mac_addr[0] = mac_hi & 0xFF;
 797         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 798         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 799         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 800         mac_addr[4] = mac_lo & 0xFF;
 801         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 802
 803         if (!getenv("ethaddr")) {
 804                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 805                 if (is_valid_ethaddr(mac_addr))
 806                         eth_setenv_enetaddr("ethaddr", mac_addr);
 807         }
 808
 809         mac_lo = readl(&cdev->macid1l);
 810         mac_hi = readl(&cdev->macid1h);
 811         mac_addr[0] = mac_hi & 0xFF;
 812         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 813         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 814         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 815         mac_addr[4] = mac_lo & 0xFF;
 816         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 817
 818         if (!getenv("eth1addr")) {
 819                 if (is_valid_ethaddr(mac_addr))
 820                         eth_setenv_enetaddr("eth1addr", mac_addr);
 821         }
 822
 823         if (board_is_eposevm()) {
 824                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 825                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 826                 cpsw_slaves[0].phy_addr = 16;
 827         } else if (board_is_sk()) {
 828                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 829                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 830                 cpsw_slaves[0].phy_addr = 4;
 831                 cpsw_slaves[1].phy_addr = 5;
 832         } else if (board_is_idk()) {
 833                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 834                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 835                 cpsw_slaves[0].phy_addr = 0;
 836         } else {
 837                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 838                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 839                 cpsw_slaves[0].phy_addr = 0;
 840         }
 841
 842         rv = cpsw_register(&cpsw_data);
 843         if (rv < 0)
 844                 printf("Error %d registering CPSW switch\n", rv);
 845
 846         return rv;
 847 }
 848 #endif