git.sur5r.net Git - u-boot/blob - board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  39 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  40
  41 #ifdef CONFIG_DRIVER_TI_CPSW
  42 #include <cpsw.h>
  43 #endif
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 /* GPIO 7_11 */
  48 #define GPIO_DDR_VTT_EN 203
  49
  50 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  51
  52 const struct omap_sysinfo sysinfo = {
  53         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  54 };
  55
  56 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  57         .dmm_lisa_map_3 = 0x80740300,
  58         .is_ma_present  = 0x1
  59 };
  60
  61 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  62 {
  63         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  64 }
  65
  66 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  67         .sdram_config_init              = 0x61851b32,
  68         .sdram_config                   = 0x61851b32,
  69         .sdram_config2                  = 0x08000000,
  70         .ref_ctrl                       = 0x000040F1,
  71         .ref_ctrl_final                 = 0x00001035,
  72         .sdram_tim1                     = 0xcccf36ab,
  73         .sdram_tim2                     = 0x308f7fda,
  74         .sdram_tim3                     = 0x409f88a8,
  75         .read_idle_ctrl                 = 0x00050000,
  76         .zq_config                      = 0x5007190b,
  77         .temp_alert_config              = 0x00000000,
  78         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
  79         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
  80         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  81         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  82         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  83         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
  84         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
  85         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  86         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  87         .emif_rd_wr_lvl_ctl             = 0x00000000,
  88         .emif_rd_wr_exec_thresh         = 0x00000305
  89 };
  90
  91 /* Ext phy ctrl regs 1-35 */
  92 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  93         0x10040100,
  94         0x00910091,
  95         0x00950095,
  96         0x009B009B,
  97         0x009E009E,
  98         0x00980098,
  99         0x00340034,
 100         0x00350035,
 101         0x00340034,
 102         0x00310031,
 103         0x00340034,
 104         0x007F007F,
 105         0x007F007F,
 106         0x007F007F,
 107         0x007F007F,
 108         0x007F007F,
 109         0x00480048,
 110         0x004A004A,
 111         0x00520052,
 112         0x00550055,
 113         0x00500050,
 114         0x00000000,
 115         0x00600020,
 116         0x40011080,
 117         0x08102040,
 118         0x0,
 119         0x0,
 120         0x0,
 121         0x0,
 122         0x0,
 123         0x0,
 124         0x0,
 125         0x0,
 126         0x0,
 127         0x0
 128 };
 129
 130 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 131         .sdram_config_init              = 0x61851b32,
 132         .sdram_config                   = 0x61851b32,
 133         .sdram_config2                  = 0x08000000,
 134         .ref_ctrl                       = 0x000040F1,
 135         .ref_ctrl_final                 = 0x00001035,
 136         .sdram_tim1                     = 0xcccf36b3,
 137         .sdram_tim2                     = 0x308f7fda,
 138         .sdram_tim3                     = 0x407f88a8,
 139         .read_idle_ctrl                 = 0x00050000,
 140         .zq_config                      = 0x5007190b,
 141         .temp_alert_config              = 0x00000000,
 142         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 143         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 144         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 145         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 146         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 147         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 148         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 149         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 150         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 151         .emif_rd_wr_lvl_ctl             = 0x00000000,
 152         .emif_rd_wr_exec_thresh         = 0x00000305
 153 };
 154
 155 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 156         0x10040100,
 157         0x00910091,
 158         0x00950095,
 159         0x009B009B,
 160         0x009E009E,
 161         0x00980098,
 162         0x00340034,
 163         0x00350035,
 164         0x00340034,
 165         0x00310031,
 166         0x00340034,
 167         0x007F007F,
 168         0x007F007F,
 169         0x007F007F,
 170         0x007F007F,
 171         0x007F007F,
 172         0x00480048,
 173         0x004A004A,
 174         0x00520052,
 175         0x00550055,
 176         0x00500050,
 177         0x00000000,
 178         0x00600020,
 179         0x40011080,
 180         0x08102040,
 181         0x0,
 182         0x0,
 183         0x0,
 184         0x0,
 185         0x0,
 186         0x0,
 187         0x0,
 188         0x0,
 189         0x0,
 190         0x0
 191 };
 192
 193 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 194 {
 195         switch (emif_nr) {
 196         case 1:
 197                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 198                 break;
 199         case 2:
 200                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 201                 break;
 202         }
 203 }
 204
 205 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 206 {
 207         switch (emif_nr) {
 208         case 1:
 209                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 210                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 211                 break;
 212         case 2:
 213                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 214                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 215                 break;
 216         }
 217 }
 218
 219 struct vcores_data beagle_x15_volts = {
 220         .mpu.value              = VDD_MPU_DRA7,
 221         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU,
 222         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 223         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 224         .mpu.pmic               = &tps659038,
 225         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 226
 227         .eve.value              = VDD_EVE_DRA7,
 228         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE,
 229         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 230         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 231         .eve.pmic               = &tps659038,
 232         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 233
 234         .gpu.value              = VDD_GPU_DRA7,
 235         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU,
 236         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 237         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 238         .gpu.pmic               = &tps659038,
 239         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 240
 241         .core.value             = VDD_CORE_DRA7,
 242         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE,
 243         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 244         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 245         .core.pmic              = &tps659038,
 246
 247         .iva.value              = VDD_IVA_DRA7,
 248         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA,
 249         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 250         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 251         .iva.pmic               = &tps659038,
 252         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 253 };
 254
 255 struct vcores_data am572x_idk_volts = {
 256         .mpu.value              = VDD_MPU_DRA7,
 257         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU,
 258         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 259         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 260         .mpu.pmic               = &tps659038,
 261         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 262
 263         .eve.value              = VDD_EVE_DRA7,
 264         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE,
 265         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 266         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 267         .eve.pmic               = &tps659038,
 268         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 269
 270         .gpu.value              = VDD_GPU_DRA7,
 271         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU,
 272         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 273         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 274         .gpu.pmic               = &tps659038,
 275         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 276
 277         .core.value             = VDD_CORE_DRA7,
 278         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE,
 279         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 280         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 281         .core.pmic              = &tps659038,
 282
 283         .iva.value              = VDD_IVA_DRA7,
 284         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA,
 285         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 286         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 287         .iva.pmic               = &tps659038,
 288         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 289 };
 290
 291 #ifdef CONFIG_SPL_BUILD
 292 /* No env to setup for SPL */
 293 static inline void setup_board_eeprom_env(void) { }
 294
 295 /* Override function to read eeprom information */
 296 void do_board_detect(void)
 297 {
 298         int rc;
 299
 300         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 301                                   CONFIG_EEPROM_CHIP_ADDRESS);
 302         if (rc)
 303                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 304 }
 305
 306 #else   /* CONFIG_SPL_BUILD */
 307
 308 /* Override function to read eeprom information: actual i2c read done by SPL*/
 309 void do_board_detect(void)
 310 {
 311         char *bname = NULL;
 312         int rc;
 313
 314         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 315                                   CONFIG_EEPROM_CHIP_ADDRESS);
 316         if (rc)
 317                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 318
 319         if (board_is_x15())
 320                 bname = "BeagleBoard X15";
 321         else if (board_is_am572x_evm())
 322                 bname = "AM572x EVM";
 323         else if (board_is_am572x_idk())
 324                 bname = "AM572x IDK";
 325
 326         if (bname)
 327                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 328                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 329 }
 330
 331 static void setup_board_eeprom_env(void)
 332 {
 333         char *name = "beagle_x15";
 334         int rc;
 335
 336         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 337                                   CONFIG_EEPROM_CHIP_ADDRESS);
 338         if (rc)
 339                 goto invalid_eeprom;
 340
 341         if (board_is_x15())
 342                 name = "beagle_x15";
 343         else if (board_is_am572x_evm())
 344                 name = "am57xx_evm";
 345         else if (board_is_am572x_idk())
 346                 name = "am572x_idk";
 347         else
 348                 printf("Unidentified board claims %s in eeprom header\n",
 349                        board_ti_get_name());
 350
 351 invalid_eeprom:
 352         set_board_info_env(name);
 353 }
 354
 355 #endif  /* CONFIG_SPL_BUILD */
 356
 357 void vcores_init(void)
 358 {
 359         if (board_is_am572x_idk())
 360                 *omap_vcores = &am572x_idk_volts;
 361         else
 362                 *omap_vcores = &beagle_x15_volts;
 363 }
 364
 365 void hw_data_init(void)
 366 {
 367         *prcm = &dra7xx_prcm;
 368         *dplls_data = &dra7xx_dplls;
 369         *ctrl = &dra7xx_ctrl;
 370 }
 371
 372 int board_init(void)
 373 {
 374         gpmc_init();
 375         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 376
 377         return 0;
 378 }
 379
 380 int board_late_init(void)
 381 {
 382         setup_board_eeprom_env();
 383
 384         /*
 385          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 386          * This is the POWERHOLD-in-Low behavior.
 387          */
 388         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 389         return 0;
 390 }
 391
 392 void set_muxconf_regs(void)
 393 {
 394         do_set_mux32((*ctrl)->control_padconf_core_base,
 395                      early_padconf, ARRAY_SIZE(early_padconf));
 396 }
 397
 398 #ifdef CONFIG_IODELAY_RECALIBRATION
 399 void recalibrate_iodelay(void)
 400 {
 401         const struct pad_conf_entry *pconf;
 402         const struct iodelay_cfg_entry *iod;
 403         int pconf_sz, iod_sz;
 404
 405         if (board_is_am572x_idk()) {
 406                 pconf = core_padconf_array_essential_am572x_idk;
 407                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 408                 iod = iodelay_cfg_array_am572x_idk;
 409                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 410         } else {
 411                 /* Common for X15/GPEVM */
 412                 pconf = core_padconf_array_essential_x15;
 413                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 414                 iod = iodelay_cfg_array_x15;
 415                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
 416         }
 417
 418         __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 419 }
 420 #endif
 421
 422 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 423 int board_mmc_init(bd_t *bis)
 424 {
 425         omap_mmc_init(0, 0, 0, -1, -1);
 426         omap_mmc_init(1, 0, 0, -1, -1);
 427         return 0;
 428 }
 429 #endif
 430
 431 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 432 int spl_start_uboot(void)
 433 {
 434         /* break into full u-boot on 'c' */
 435         if (serial_tstc() && serial_getc() == 'c')
 436                 return 1;
 437
 438 #ifdef CONFIG_SPL_ENV_SUPPORT
 439         env_init();
 440         env_relocate_spec();
 441         if (getenv_yesno("boot_os") != 1)
 442                 return 1;
 443 #endif
 444
 445         return 0;
 446 }
 447 #endif
 448
 449 #ifdef CONFIG_USB_DWC3
 450 static struct dwc3_device usb_otg_ss1 = {
 451         .maximum_speed = USB_SPEED_SUPER,
 452         .base = DRA7_USB_OTG_SS1_BASE,
 453         .tx_fifo_resize = false,
 454         .index = 0,
 455 };
 456
 457 static struct dwc3_omap_device usb_otg_ss1_glue = {
 458         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 459         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 460         .index = 0,
 461 };
 462
 463 static struct ti_usb_phy_device usb_phy1_device = {
 464         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 465         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 466         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 467         .index = 0,
 468 };
 469
 470 static struct dwc3_device usb_otg_ss2 = {
 471         .maximum_speed = USB_SPEED_HIGH,
 472         .base = DRA7_USB_OTG_SS2_BASE,
 473         .tx_fifo_resize = false,
 474         .index = 1,
 475 };
 476
 477 static struct dwc3_omap_device usb_otg_ss2_glue = {
 478         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 479         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 480         .index = 1,
 481 };
 482
 483 static struct ti_usb_phy_device usb_phy2_device = {
 484         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 485         .index = 1,
 486 };
 487
 488 int usb_gadget_handle_interrupts(int index)
 489 {
 490         u32 status;
 491
 492         status = dwc3_omap_uboot_interrupt_status(index);
 493         if (status)
 494                 dwc3_uboot_handle_interrupt(index);
 495
 496         return 0;
 497 }
 498 #endif /* CONFIG_USB_DWC3 */
 499
 500 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 501 int board_usb_init(int index, enum usb_init_type init)
 502 {
 503         enable_usb_clocks(index);
 504         switch (index) {
 505         case 0:
 506                 if (init == USB_INIT_DEVICE) {
 507                         printf("port %d can't be used as device\n", index);
 508                         disable_usb_clocks(index);
 509                         return -EINVAL;
 510                 }
 511                 break;
 512         case 1:
 513                 if (init == USB_INIT_DEVICE) {
 514 #ifdef CONFIG_USB_DWC3
 515                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 516                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 517                         ti_usb_phy_uboot_init(&usb_phy2_device);
 518                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 519                         dwc3_uboot_init(&usb_otg_ss2);
 520 #endif
 521                 } else {
 522                         printf("port %d can't be used as host\n", index);
 523                         disable_usb_clocks(index);
 524                         return -EINVAL;
 525                 }
 526
 527                 break;
 528         default:
 529                 printf("Invalid Controller Index\n");
 530         }
 531
 532         return 0;
 533 }
 534
 535 int board_usb_cleanup(int index, enum usb_init_type init)
 536 {
 537 #ifdef CONFIG_USB_DWC3
 538         switch (index) {
 539         case 0:
 540         case 1:
 541                 if (init == USB_INIT_DEVICE) {
 542                         ti_usb_phy_uboot_exit(index);
 543                         dwc3_uboot_exit(index);
 544                         dwc3_omap_uboot_exit(index);
 545                 }
 546                 break;
 547         default:
 548                 printf("Invalid Controller Index\n");
 549         }
 550 #endif
 551         disable_usb_clocks(index);
 552         return 0;
 553 }
 554 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 555
 556 #ifdef CONFIG_DRIVER_TI_CPSW
 557
 558 /* Delay value to add to calibrated value */
 559 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 560 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 561 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 562 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 563 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 564 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 565 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 566 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 567 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 568 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 569
 570 static void cpsw_control(int enabled)
 571 {
 572         /* VTP can be added here */
 573 }
 574
 575 static struct cpsw_slave_data cpsw_slaves[] = {
 576         {
 577                 .slave_reg_ofs  = 0x208,
 578                 .sliver_reg_ofs = 0xd80,
 579                 .phy_addr       = 1,
 580         },
 581         {
 582                 .slave_reg_ofs  = 0x308,
 583                 .sliver_reg_ofs = 0xdc0,
 584                 .phy_addr       = 2,
 585         },
 586 };
 587
 588 static struct cpsw_platform_data cpsw_data = {
 589         .mdio_base              = CPSW_MDIO_BASE,
 590         .cpsw_base              = CPSW_BASE,
 591         .mdio_div               = 0xff,
 592         .channels               = 8,
 593         .cpdma_reg_ofs          = 0x800,
 594         .slaves                 = 1,
 595         .slave_data             = cpsw_slaves,
 596         .ale_reg_ofs            = 0xd00,
 597         .ale_entries            = 1024,
 598         .host_port_reg_ofs      = 0x108,
 599         .hw_stats_reg_ofs       = 0x900,
 600         .bd_ram_ofs             = 0x2000,
 601         .mac_control            = (1 << 5),
 602         .control                = cpsw_control,
 603         .host_port_num          = 0,
 604         .version                = CPSW_CTRL_VERSION_2,
 605 };
 606
 607 static u64 mac_to_u64(u8 mac[6])
 608 {
 609         int i;
 610         u64 addr = 0;
 611
 612         for (i = 0; i < 6; i++) {
 613                 addr <<= 8;
 614                 addr |= mac[i];
 615         }
 616
 617         return addr;
 618 }
 619
 620 static void u64_to_mac(u64 addr, u8 mac[6])
 621 {
 622         mac[5] = addr;
 623         mac[4] = addr >> 8;
 624         mac[3] = addr >> 16;
 625         mac[2] = addr >> 24;
 626         mac[1] = addr >> 32;
 627         mac[0] = addr >> 40;
 628 }
 629
 630 int board_eth_init(bd_t *bis)
 631 {
 632         int ret;
 633         uint8_t mac_addr[6];
 634         uint32_t mac_hi, mac_lo;
 635         uint32_t ctrl_val;
 636         int i;
 637         u64 mac1, mac2;
 638         u8 mac_addr1[6], mac_addr2[6];
 639         int num_macs;
 640
 641         /* try reading mac address from efuse */
 642         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 643         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 644         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 645         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 646         mac_addr[2] = mac_hi & 0xFF;
 647         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 648         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 649         mac_addr[5] = mac_lo & 0xFF;
 650
 651         if (!getenv("ethaddr")) {
 652                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 653
 654                 if (is_valid_ethaddr(mac_addr))
 655                         eth_setenv_enetaddr("ethaddr", mac_addr);
 656         }
 657
 658         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 659         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 660         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 661         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 662         mac_addr[2] = mac_hi & 0xFF;
 663         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 664         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 665         mac_addr[5] = mac_lo & 0xFF;
 666
 667         if (!getenv("eth1addr")) {
 668                 if (is_valid_ethaddr(mac_addr))
 669                         eth_setenv_enetaddr("eth1addr", mac_addr);
 670         }
 671
 672         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 673         ctrl_val |= 0x22;
 674         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 675
 676         /* The phy address for the AM572x IDK are different than x15 */
 677         if (board_is_am572x_idk()) {
 678                 cpsw_data.slave_data[0].phy_addr = 0;
 679                 cpsw_data.slave_data[1].phy_addr = 1;
 680         }
 681
 682         ret = cpsw_register(&cpsw_data);
 683         if (ret < 0)
 684                 printf("Error %d registering CPSW switch\n", ret);
 685
 686         /*
 687          * Export any Ethernet MAC addresses from EEPROM.
 688          * On AM57xx the 2 MAC addresses define the address range
 689          */
 690         board_ti_get_eth_mac_addr(0, mac_addr1);
 691         board_ti_get_eth_mac_addr(1, mac_addr2);
 692
 693         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 694                 mac1 = mac_to_u64(mac_addr1);
 695                 mac2 = mac_to_u64(mac_addr2);
 696
 697                 /* must contain an address range */
 698                 num_macs = mac2 - mac1 + 1;
 699                 /* <= 50 to protect against user programming error */
 700                 if (num_macs > 0 && num_macs <= 50) {
 701                         for (i = 0; i < num_macs; i++) {
 702                                 u64_to_mac(mac1 + i, mac_addr);
 703                                 if (is_valid_ethaddr(mac_addr)) {
 704                                         eth_setenv_enetaddr_by_index("eth",
 705                                                                      i + 2,
 706                                                                      mac_addr);
 707                                 }
 708                         }
 709                 }
 710         }
 711
 712         return ret;
 713 }
 714 #endif
 715
 716 #ifdef CONFIG_BOARD_EARLY_INIT_F
 717 /* VTT regulator enable */
 718 static inline void vtt_regulator_enable(void)
 719 {
 720         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 721                 return;
 722
 723         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 724         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 725 }
 726
 727 int board_early_init_f(void)
 728 {
 729         vtt_regulator_enable();
 730         return 0;
 731 }
 732 #endif
 733
 734 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 735 int ft_board_setup(void *blob, bd_t *bd)
 736 {
 737         ft_cpu_setup(blob, bd);
 738
 739         return 0;
 740 }
 741 #endif
 742
 743 #ifdef CONFIG_SPL_LOAD_FIT
 744 int board_fit_config_name_match(const char *name)
 745 {
 746         if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
 747                 return 0;
 748         else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
 749                 return 0;
 750         else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
 751                 return 0;
 752         else
 753                 return -1;
 754 }
 755 #endif
 756
 757 #ifdef CONFIG_TI_SECURE_DEVICE
 758 void board_fit_image_post_process(void **p_image, size_t *p_size)
 759 {
 760         secure_boot_verify_image(p_image, p_size);
 761 }
 762 #endif