git.sur5r.net Git - u-boot/blob - board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/omap.h>
  26 #include <environment.h>
  27 #include <usb.h>
  28 #include <linux/usb/gadget.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32
  33 #include "../common/board_detect.h"
  34 #include "mux_data.h"
  35
  36 #define board_is_x15()          board_ti_is("BBRDX15_")
  37 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  38 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  39
  40 #ifdef CONFIG_DRIVER_TI_CPSW
  41 #include <cpsw.h>
  42 #endif
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO 7_11 */
  47 #define GPIO_DDR_VTT_EN 203
  48
  49 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  50
  51 const struct omap_sysinfo sysinfo = {
  52         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  53 };
  54
  55 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  56         .dmm_lisa_map_3 = 0x80740300,
  57         .is_ma_present  = 0x1
  58 };
  59
  60 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  61 {
  62         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  63 }
  64
  65 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  66         .sdram_config_init              = 0x61851b32,
  67         .sdram_config                   = 0x61851b32,
  68         .sdram_config2                  = 0x08000000,
  69         .ref_ctrl                       = 0x000040F1,
  70         .ref_ctrl_final                 = 0x00001035,
  71         .sdram_tim1                     = 0xcccf36ab,
  72         .sdram_tim2                     = 0x308f7fda,
  73         .sdram_tim3                     = 0x409f88a8,
  74         .read_idle_ctrl                 = 0x00050000,
  75         .zq_config                      = 0x5007190b,
  76         .temp_alert_config              = 0x00000000,
  77         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
  78         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
  79         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  80         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  81         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  82         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
  83         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
  84         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  85         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  86         .emif_rd_wr_lvl_ctl             = 0x00000000,
  87         .emif_rd_wr_exec_thresh         = 0x00000305
  88 };
  89
  90 /* Ext phy ctrl regs 1-35 */
  91 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  92         0x10040100,
  93         0x00910091,
  94         0x00950095,
  95         0x009B009B,
  96         0x009E009E,
  97         0x00980098,
  98         0x00340034,
  99         0x00350035,
 100         0x00340034,
 101         0x00310031,
 102         0x00340034,
 103         0x007F007F,
 104         0x007F007F,
 105         0x007F007F,
 106         0x007F007F,
 107         0x007F007F,
 108         0x00480048,
 109         0x004A004A,
 110         0x00520052,
 111         0x00550055,
 112         0x00500050,
 113         0x00000000,
 114         0x00600020,
 115         0x40011080,
 116         0x08102040,
 117         0x0,
 118         0x0,
 119         0x0,
 120         0x0,
 121         0x0,
 122         0x0,
 123         0x0,
 124         0x0,
 125         0x0,
 126         0x0
 127 };
 128
 129 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 130         .sdram_config_init              = 0x61851b32,
 131         .sdram_config                   = 0x61851b32,
 132         .sdram_config2                  = 0x08000000,
 133         .ref_ctrl                       = 0x000040F1,
 134         .ref_ctrl_final                 = 0x00001035,
 135         .sdram_tim1                     = 0xcccf36b3,
 136         .sdram_tim2                     = 0x308f7fda,
 137         .sdram_tim3                     = 0x407f88a8,
 138         .read_idle_ctrl                 = 0x00050000,
 139         .zq_config                      = 0x5007190b,
 140         .temp_alert_config              = 0x00000000,
 141         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 142         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 143         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 144         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 145         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 146         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 147         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 148         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 149         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 150         .emif_rd_wr_lvl_ctl             = 0x00000000,
 151         .emif_rd_wr_exec_thresh         = 0x00000305
 152 };
 153
 154 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 155         0x10040100,
 156         0x00910091,
 157         0x00950095,
 158         0x009B009B,
 159         0x009E009E,
 160         0x00980098,
 161         0x00340034,
 162         0x00350035,
 163         0x00340034,
 164         0x00310031,
 165         0x00340034,
 166         0x007F007F,
 167         0x007F007F,
 168         0x007F007F,
 169         0x007F007F,
 170         0x007F007F,
 171         0x00480048,
 172         0x004A004A,
 173         0x00520052,
 174         0x00550055,
 175         0x00500050,
 176         0x00000000,
 177         0x00600020,
 178         0x40011080,
 179         0x08102040,
 180         0x0,
 181         0x0,
 182         0x0,
 183         0x0,
 184         0x0,
 185         0x0,
 186         0x0,
 187         0x0,
 188         0x0,
 189         0x0
 190 };
 191
 192 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 193 {
 194         switch (emif_nr) {
 195         case 1:
 196                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 197                 break;
 198         case 2:
 199                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 200                 break;
 201         }
 202 }
 203
 204 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 205 {
 206         switch (emif_nr) {
 207         case 1:
 208                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 209                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 210                 break;
 211         case 2:
 212                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 213                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 214                 break;
 215         }
 216 }
 217
 218 struct vcores_data beagle_x15_volts = {
 219         .mpu.value              = VDD_MPU_DRA7,
 220         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU,
 221         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 222         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 223         .mpu.pmic               = &tps659038,
 224         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 225
 226         .eve.value              = VDD_EVE_DRA7,
 227         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE,
 228         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 229         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 230         .eve.pmic               = &tps659038,
 231         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 232
 233         .gpu.value              = VDD_GPU_DRA7,
 234         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU,
 235         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 236         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 237         .gpu.pmic               = &tps659038,
 238         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 239
 240         .core.value             = VDD_CORE_DRA7,
 241         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE,
 242         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 243         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 244         .core.pmic              = &tps659038,
 245
 246         .iva.value              = VDD_IVA_DRA7,
 247         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA,
 248         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 249         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 250         .iva.pmic               = &tps659038,
 251         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 252 };
 253
 254 struct vcores_data am572x_idk_volts = {
 255         .mpu.value              = VDD_MPU_DRA7,
 256         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU,
 257         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 258         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 259         .mpu.pmic               = &tps659038,
 260         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 261
 262         .eve.value              = VDD_EVE_DRA7,
 263         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE,
 264         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 265         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 266         .eve.pmic               = &tps659038,
 267         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 268
 269         .gpu.value              = VDD_GPU_DRA7,
 270         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU,
 271         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 272         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 273         .gpu.pmic               = &tps659038,
 274         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 275
 276         .core.value             = VDD_CORE_DRA7,
 277         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE,
 278         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 279         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 280         .core.pmic              = &tps659038,
 281
 282         .iva.value              = VDD_IVA_DRA7,
 283         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA,
 284         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 285         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 286         .iva.pmic               = &tps659038,
 287         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 288 };
 289
 290 #ifdef CONFIG_SPL_BUILD
 291 /* No env to setup for SPL */
 292 static inline void setup_board_eeprom_env(void) { }
 293
 294 /* Override function to read eeprom information */
 295 void do_board_detect(void)
 296 {
 297         int rc;
 298
 299         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 300                                   CONFIG_EEPROM_CHIP_ADDRESS);
 301         if (rc)
 302                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 303 }
 304
 305 #else   /* CONFIG_SPL_BUILD */
 306
 307 /* Override function to read eeprom information: actual i2c read done by SPL*/
 308 void do_board_detect(void)
 309 {
 310         char *bname = NULL;
 311         int rc;
 312
 313         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 314                                   CONFIG_EEPROM_CHIP_ADDRESS);
 315         if (rc)
 316                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 317
 318         if (board_is_x15())
 319                 bname = "BeagleBoard X15";
 320         else if (board_is_am572x_evm())
 321                 bname = "AM572x EVM";
 322         else if (board_is_am572x_idk())
 323                 bname = "AM572x IDK";
 324
 325         if (bname)
 326                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 327                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 328 }
 329
 330 static void setup_board_eeprom_env(void)
 331 {
 332         char *name = "beagle_x15";
 333         int rc;
 334
 335         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 336                                   CONFIG_EEPROM_CHIP_ADDRESS);
 337         if (rc)
 338                 goto invalid_eeprom;
 339
 340         if (board_is_am572x_evm())
 341                 name = "am57xx_evm";
 342         else if (board_is_am572x_idk())
 343                 name = "am572x_idk";
 344         else
 345                 printf("Unidentified board claims %s in eeprom header\n",
 346                        board_ti_get_name());
 347
 348 invalid_eeprom:
 349         set_board_info_env(name);
 350 }
 351
 352 #endif  /* CONFIG_SPL_BUILD */
 353
 354 void vcores_init(void)
 355 {
 356         if (board_is_am572x_idk())
 357                 *omap_vcores = &am572x_idk_volts;
 358         else
 359                 *omap_vcores = &beagle_x15_volts;
 360 }
 361
 362 void hw_data_init(void)
 363 {
 364         *prcm = &dra7xx_prcm;
 365         *dplls_data = &dra7xx_dplls;
 366         *ctrl = &dra7xx_ctrl;
 367 }
 368
 369 int board_init(void)
 370 {
 371         gpmc_init();
 372         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 373
 374         return 0;
 375 }
 376
 377 int board_late_init(void)
 378 {
 379         setup_board_eeprom_env();
 380
 381         /*
 382          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 383          * This is the POWERHOLD-in-Low behavior.
 384          */
 385         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 386         return 0;
 387 }
 388
 389 void set_muxconf_regs(void)
 390 {
 391         do_set_mux32((*ctrl)->control_padconf_core_base,
 392                      early_padconf, ARRAY_SIZE(early_padconf));
 393 }
 394
 395 #ifdef CONFIG_IODELAY_RECALIBRATION
 396 void recalibrate_iodelay(void)
 397 {
 398         const struct pad_conf_entry *pconf;
 399         const struct iodelay_cfg_entry *iod;
 400         int pconf_sz, iod_sz;
 401
 402         if (board_is_am572x_idk()) {
 403                 pconf = core_padconf_array_essential_am572x_idk;
 404                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 405                 iod = iodelay_cfg_array_am572x_idk;
 406                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 407         } else {
 408                 /* Common for X15/GPEVM */
 409                 pconf = core_padconf_array_essential_x15;
 410                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 411                 iod = iodelay_cfg_array_x15;
 412                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
 413         }
 414
 415         __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 416 }
 417 #endif
 418
 419 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 420 int board_mmc_init(bd_t *bis)
 421 {
 422         omap_mmc_init(0, 0, 0, -1, -1);
 423         omap_mmc_init(1, 0, 0, -1, -1);
 424         return 0;
 425 }
 426 #endif
 427
 428 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 429 int spl_start_uboot(void)
 430 {
 431         /* break into full u-boot on 'c' */
 432         if (serial_tstc() && serial_getc() == 'c')
 433                 return 1;
 434
 435 #ifdef CONFIG_SPL_ENV_SUPPORT
 436         env_init();
 437         env_relocate_spec();
 438         if (getenv_yesno("boot_os") != 1)
 439                 return 1;
 440 #endif
 441
 442         return 0;
 443 }
 444 #endif
 445
 446 #ifdef CONFIG_USB_DWC3
 447 static struct dwc3_device usb_otg_ss1 = {
 448         .maximum_speed = USB_SPEED_SUPER,
 449         .base = DRA7_USB_OTG_SS1_BASE,
 450         .tx_fifo_resize = false,
 451         .index = 0,
 452 };
 453
 454 static struct dwc3_omap_device usb_otg_ss1_glue = {
 455         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 456         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 457         .index = 0,
 458 };
 459
 460 static struct ti_usb_phy_device usb_phy1_device = {
 461         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 462         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 463         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 464         .index = 0,
 465 };
 466
 467 static struct dwc3_device usb_otg_ss2 = {
 468         .maximum_speed = USB_SPEED_HIGH,
 469         .base = DRA7_USB_OTG_SS2_BASE,
 470         .tx_fifo_resize = false,
 471         .index = 1,
 472 };
 473
 474 static struct dwc3_omap_device usb_otg_ss2_glue = {
 475         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 476         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 477         .index = 1,
 478 };
 479
 480 static struct ti_usb_phy_device usb_phy2_device = {
 481         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 482         .index = 1,
 483 };
 484
 485 int usb_gadget_handle_interrupts(int index)
 486 {
 487         u32 status;
 488
 489         status = dwc3_omap_uboot_interrupt_status(index);
 490         if (status)
 491                 dwc3_uboot_handle_interrupt(index);
 492
 493         return 0;
 494 }
 495 #endif /* CONFIG_USB_DWC3 */
 496
 497 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 498 int board_usb_init(int index, enum usb_init_type init)
 499 {
 500         enable_usb_clocks(index);
 501         switch (index) {
 502         case 0:
 503                 if (init == USB_INIT_DEVICE) {
 504                         printf("port %d can't be used as device\n", index);
 505                         disable_usb_clocks(index);
 506                         return -EINVAL;
 507                 }
 508                 break;
 509         case 1:
 510                 if (init == USB_INIT_DEVICE) {
 511 #ifdef CONFIG_USB_DWC3
 512                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 513                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 514                         ti_usb_phy_uboot_init(&usb_phy2_device);
 515                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 516                         dwc3_uboot_init(&usb_otg_ss2);
 517 #endif
 518                 } else {
 519                         printf("port %d can't be used as host\n", index);
 520                         disable_usb_clocks(index);
 521                         return -EINVAL;
 522                 }
 523
 524                 break;
 525         default:
 526                 printf("Invalid Controller Index\n");
 527         }
 528
 529         return 0;
 530 }
 531
 532 int board_usb_cleanup(int index, enum usb_init_type init)
 533 {
 534 #ifdef CONFIG_USB_DWC3
 535         switch (index) {
 536         case 0:
 537         case 1:
 538                 if (init == USB_INIT_DEVICE) {
 539                         ti_usb_phy_uboot_exit(index);
 540                         dwc3_uboot_exit(index);
 541                         dwc3_omap_uboot_exit(index);
 542                 }
 543                 break;
 544         default:
 545                 printf("Invalid Controller Index\n");
 546         }
 547 #endif
 548         disable_usb_clocks(index);
 549         return 0;
 550 }
 551 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 552
 553 #ifdef CONFIG_DRIVER_TI_CPSW
 554
 555 /* Delay value to add to calibrated value */
 556 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 557 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 558 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 559 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 560 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 561 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 562 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 563 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 564 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 565 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 566
 567 static void cpsw_control(int enabled)
 568 {
 569         /* VTP can be added here */
 570 }
 571
 572 static struct cpsw_slave_data cpsw_slaves[] = {
 573         {
 574                 .slave_reg_ofs  = 0x208,
 575                 .sliver_reg_ofs = 0xd80,
 576                 .phy_addr       = 1,
 577         },
 578         {
 579                 .slave_reg_ofs  = 0x308,
 580                 .sliver_reg_ofs = 0xdc0,
 581                 .phy_addr       = 2,
 582         },
 583 };
 584
 585 static struct cpsw_platform_data cpsw_data = {
 586         .mdio_base              = CPSW_MDIO_BASE,
 587         .cpsw_base              = CPSW_BASE,
 588         .mdio_div               = 0xff,
 589         .channels               = 8,
 590         .cpdma_reg_ofs          = 0x800,
 591         .slaves                 = 1,
 592         .slave_data             = cpsw_slaves,
 593         .ale_reg_ofs            = 0xd00,
 594         .ale_entries            = 1024,
 595         .host_port_reg_ofs      = 0x108,
 596         .hw_stats_reg_ofs       = 0x900,
 597         .bd_ram_ofs             = 0x2000,
 598         .mac_control            = (1 << 5),
 599         .control                = cpsw_control,
 600         .host_port_num          = 0,
 601         .version                = CPSW_CTRL_VERSION_2,
 602 };
 603
 604 static u64 mac_to_u64(u8 mac[6])
 605 {
 606         int i;
 607         u64 addr = 0;
 608
 609         for (i = 0; i < 6; i++) {
 610                 addr <<= 8;
 611                 addr |= mac[i];
 612         }
 613
 614         return addr;
 615 }
 616
 617 static void u64_to_mac(u64 addr, u8 mac[6])
 618 {
 619         mac[5] = addr;
 620         mac[4] = addr >> 8;
 621         mac[3] = addr >> 16;
 622         mac[2] = addr >> 24;
 623         mac[1] = addr >> 32;
 624         mac[0] = addr >> 40;
 625 }
 626
 627 int board_eth_init(bd_t *bis)
 628 {
 629         int ret;
 630         uint8_t mac_addr[6];
 631         uint32_t mac_hi, mac_lo;
 632         uint32_t ctrl_val;
 633         int i;
 634         u64 mac1, mac2;
 635         u8 mac_addr1[6], mac_addr2[6];
 636         int num_macs;
 637
 638         /* try reading mac address from efuse */
 639         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 640         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 641         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 642         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 643         mac_addr[2] = mac_hi & 0xFF;
 644         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 645         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 646         mac_addr[5] = mac_lo & 0xFF;
 647
 648         if (!getenv("ethaddr")) {
 649                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 650
 651                 if (is_valid_ethaddr(mac_addr))
 652                         eth_setenv_enetaddr("ethaddr", mac_addr);
 653         }
 654
 655         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 656         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 657         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 658         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 659         mac_addr[2] = mac_hi & 0xFF;
 660         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 661         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 662         mac_addr[5] = mac_lo & 0xFF;
 663
 664         if (!getenv("eth1addr")) {
 665                 if (is_valid_ethaddr(mac_addr))
 666                         eth_setenv_enetaddr("eth1addr", mac_addr);
 667         }
 668
 669         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 670         ctrl_val |= 0x22;
 671         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 672
 673         /* The phy address for the AM572x IDK are different than x15 */
 674         if (board_is_am572x_idk()) {
 675                 cpsw_data.slave_data[0].phy_addr = 0;
 676                 cpsw_data.slave_data[1].phy_addr = 1;
 677         }
 678
 679         ret = cpsw_register(&cpsw_data);
 680         if (ret < 0)
 681                 printf("Error %d registering CPSW switch\n", ret);
 682
 683         /*
 684          * Export any Ethernet MAC addresses from EEPROM.
 685          * On AM57xx the 2 MAC addresses define the address range
 686          */
 687         board_ti_get_eth_mac_addr(0, mac_addr1);
 688         board_ti_get_eth_mac_addr(1, mac_addr2);
 689
 690         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 691                 mac1 = mac_to_u64(mac_addr1);
 692                 mac2 = mac_to_u64(mac_addr2);
 693
 694                 /* must contain an address range */
 695                 num_macs = mac2 - mac1 + 1;
 696                 /* <= 50 to protect against user programming error */
 697                 if (num_macs > 0 && num_macs <= 50) {
 698                         for (i = 0; i < num_macs; i++) {
 699                                 u64_to_mac(mac1 + i, mac_addr);
 700                                 if (is_valid_ethaddr(mac_addr)) {
 701                                         eth_setenv_enetaddr_by_index("eth",
 702                                                                      i + 2,
 703                                                                      mac_addr);
 704                                 }
 705                         }
 706                 }
 707         }
 708
 709         return ret;
 710 }
 711 #endif
 712
 713 #ifdef CONFIG_BOARD_EARLY_INIT_F
 714 /* VTT regulator enable */
 715 static inline void vtt_regulator_enable(void)
 716 {
 717         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 718                 return;
 719
 720         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 721         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 722 }
 723
 724 int board_early_init_f(void)
 725 {
 726         vtt_regulator_enable();
 727         return 0;
 728 }
 729 #endif
 730
 731 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 732 int ft_board_setup(void *blob, bd_t *bd)
 733 {
 734         ft_cpu_setup(blob, bd);
 735
 736         return 0;
 737 }
 738 #endif
 739
 740 #ifdef CONFIG_SPL_LOAD_FIT
 741 int board_fit_config_name_match(const char *name)
 742 {
 743         if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
 744                 return 0;
 745         else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
 746                 return 0;
 747         else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
 748                 return 0;
 749         else
 750                 return -1;
 751 }
 752 #endif