git.sur5r.net Git - u-boot/blob - board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  (strncmp("B.10", board_ti_get_rev(), 3) <= 0))
  40 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  41 #define board_is_am572x_evm_reva3()     \
  42                                 (board_ti_is("AM572PM_") && \
  43                                  (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
  44 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  45 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  46
  47 #ifdef CONFIG_DRIVER_TI_CPSW
  48 #include <cpsw.h>
  49 #endif
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  54 /* GPIO 7_11 */
  55 #define GPIO_DDR_VTT_EN 203
  56
  57 /* Touch screen controller to identify the LCD */
  58 #define OSD_TS_FT_BUS_ADDRESS   0
  59 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  60 #define OSD_TS_FT_REG_ID        0xA3
  61 /*
  62  * Touchscreen IDs for various OSD panels
  63  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  64  */
  65 /* Used on newer osd101t2587 Panels */
  66 #define OSD_TS_FT_ID_5x46       0x54
  67 /* Used on older osd101t2045 Panels */
  68 #define OSD_TS_FT_ID_5606       0x08
  69
  70 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  71
  72 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  73 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  74
  75 const struct omap_sysinfo sysinfo = {
  76         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  77 };
  78
  79 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  80         .dmm_lisa_map_3 = 0x80740300,
  81         .is_ma_present  = 0x1
  82 };
  83
  84 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  85         .dmm_lisa_map_3 = 0x80640100,
  86         .is_ma_present  = 0x1
  87 };
  88
  89 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  90 {
  91         if (board_is_am571x_idk())
  92                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
  93         else
  94                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
  95 }
  96
  97 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  98         .sdram_config_init              = 0x61851b32,
  99         .sdram_config                   = 0x61851b32,
 100         .sdram_config2                  = 0x08000000,
 101         .ref_ctrl                       = 0x000040F1,
 102         .ref_ctrl_final                 = 0x00001035,
 103         .sdram_tim1                     = 0xcccf36ab,
 104         .sdram_tim2                     = 0x308f7fda,
 105         .sdram_tim3                     = 0x409f88a8,
 106         .read_idle_ctrl                 = 0x00050000,
 107         .zq_config                      = 0x5007190b,
 108         .temp_alert_config              = 0x00000000,
 109         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 110         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 111         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 112         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 113         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 114         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 115         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 116         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 117         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 118         .emif_rd_wr_lvl_ctl             = 0x00000000,
 119         .emif_rd_wr_exec_thresh         = 0x00000305
 120 };
 121
 122 /* Ext phy ctrl regs 1-35 */
 123 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 124         0x10040100,
 125         0x00910091,
 126         0x00950095,
 127         0x009B009B,
 128         0x009E009E,
 129         0x00980098,
 130         0x00340034,
 131         0x00350035,
 132         0x00340034,
 133         0x00310031,
 134         0x00340034,
 135         0x007F007F,
 136         0x007F007F,
 137         0x007F007F,
 138         0x007F007F,
 139         0x007F007F,
 140         0x00480048,
 141         0x004A004A,
 142         0x00520052,
 143         0x00550055,
 144         0x00500050,
 145         0x00000000,
 146         0x00600020,
 147         0x40011080,
 148         0x08102040,
 149         0x0,
 150         0x0,
 151         0x0,
 152         0x0,
 153         0x0,
 154         0x0,
 155         0x0,
 156         0x0,
 157         0x0,
 158         0x0
 159 };
 160
 161 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 162         .sdram_config_init              = 0x61851b32,
 163         .sdram_config                   = 0x61851b32,
 164         .sdram_config2                  = 0x08000000,
 165         .ref_ctrl                       = 0x000040F1,
 166         .ref_ctrl_final                 = 0x00001035,
 167         .sdram_tim1                     = 0xcccf36b3,
 168         .sdram_tim2                     = 0x308f7fda,
 169         .sdram_tim3                     = 0x407f88a8,
 170         .read_idle_ctrl                 = 0x00050000,
 171         .zq_config                      = 0x5007190b,
 172         .temp_alert_config              = 0x00000000,
 173         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 174         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 175         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 176         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 177         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 178         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 179         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 180         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 181         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 182         .emif_rd_wr_lvl_ctl             = 0x00000000,
 183         .emif_rd_wr_exec_thresh         = 0x00000305
 184 };
 185
 186 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 187         0x10040100,
 188         0x00910091,
 189         0x00950095,
 190         0x009B009B,
 191         0x009E009E,
 192         0x00980098,
 193         0x00340034,
 194         0x00350035,
 195         0x00340034,
 196         0x00310031,
 197         0x00340034,
 198         0x007F007F,
 199         0x007F007F,
 200         0x007F007F,
 201         0x007F007F,
 202         0x007F007F,
 203         0x00480048,
 204         0x004A004A,
 205         0x00520052,
 206         0x00550055,
 207         0x00500050,
 208         0x00000000,
 209         0x00600020,
 210         0x40011080,
 211         0x08102040,
 212         0x0,
 213         0x0,
 214         0x0,
 215         0x0,
 216         0x0,
 217         0x0,
 218         0x0,
 219         0x0,
 220         0x0,
 221         0x0
 222 };
 223
 224 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 225 {
 226         switch (emif_nr) {
 227         case 1:
 228                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 229                 break;
 230         case 2:
 231                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 232                 break;
 233         }
 234 }
 235
 236 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 237 {
 238         switch (emif_nr) {
 239         case 1:
 240                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 241                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 242                 break;
 243         case 2:
 244                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 245                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 246                 break;
 247         }
 248 }
 249
 250 struct vcores_data beagle_x15_volts = {
 251         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 252         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 253         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 254         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 255         .mpu.pmic               = &tps659038,
 256         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 257
 258         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 259         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 260         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 261         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 262         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 263         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 264         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 265         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 266         .eve.pmic               = &tps659038,
 267         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 268
 269         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 270         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 271         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 272         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 273         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 274         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 275         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 276         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 277         .gpu.pmic               = &tps659038,
 278         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 279
 280         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 281         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 282         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 283         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 284         .core.pmic              = &tps659038,
 285
 286         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 287         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 288         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 289         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 290         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 291         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 292         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 293         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 294         .iva.pmic               = &tps659038,
 295         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 296 };
 297
 298 struct vcores_data am572x_idk_volts = {
 299         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 300         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 301         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 302         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 303         .mpu.pmic               = &tps659038,
 304         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 305
 306         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 307         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 308         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 309         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 310         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 311         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 312         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 313         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 314         .eve.pmic               = &tps659038,
 315         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 316
 317         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 318         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 319         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 320         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 321         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 322         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 323         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 324         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 325         .gpu.pmic               = &tps659038,
 326         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 327
 328         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 329         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 330         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 331         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 332         .core.pmic              = &tps659038,
 333
 334         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 335         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 336         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 337         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 338         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 339         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 340         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 341         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 342         .iva.pmic               = &tps659038,
 343         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 344 };
 345
 346 struct vcores_data am571x_idk_volts = {
 347         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 348         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 349         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 350         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 351         .mpu.pmic               = &tps659038,
 352         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 353
 354         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 355         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 356         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 357         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 358         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 359         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 360         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 361         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 362         .eve.pmic               = &tps659038,
 363         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 364
 365         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 366         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 367         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 368         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 369         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 370         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 371         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 372         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 373         .gpu.pmic               = &tps659038,
 374         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 375
 376         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 377         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 378         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 379         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 380         .core.pmic              = &tps659038,
 381
 382         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 383         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 384         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 385         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 386         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 387         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 388         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 389         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 390         .iva.pmic               = &tps659038,
 391         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 392 };
 393
 394 int get_voltrail_opp(int rail_offset)
 395 {
 396         int opp;
 397
 398         switch (rail_offset) {
 399         case VOLT_MPU:
 400                 opp = DRA7_MPU_OPP;
 401                 break;
 402         case VOLT_CORE:
 403                 opp = DRA7_CORE_OPP;
 404                 break;
 405         case VOLT_GPU:
 406                 opp = DRA7_GPU_OPP;
 407                 break;
 408         case VOLT_EVE:
 409                 opp = DRA7_DSPEVE_OPP;
 410                 break;
 411         case VOLT_IVA:
 412                 opp = DRA7_IVA_OPP;
 413                 break;
 414         default:
 415                 opp = OPP_NOM;
 416         }
 417
 418         return opp;
 419 }
 420
 421
 422 #ifdef CONFIG_SPL_BUILD
 423 /* No env to setup for SPL */
 424 static inline void setup_board_eeprom_env(void) { }
 425
 426 /* Override function to read eeprom information */
 427 void do_board_detect(void)
 428 {
 429         int rc;
 430
 431         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 432                                   CONFIG_EEPROM_CHIP_ADDRESS);
 433         if (rc)
 434                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 435 }
 436
 437 #else   /* CONFIG_SPL_BUILD */
 438
 439 /* Override function to read eeprom information: actual i2c read done by SPL*/
 440 void do_board_detect(void)
 441 {
 442         char *bname = NULL;
 443         int rc;
 444
 445         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 446                                   CONFIG_EEPROM_CHIP_ADDRESS);
 447         if (rc)
 448                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 449
 450         if (board_is_x15())
 451                 bname = "BeagleBoard X15";
 452         else if (board_is_am572x_evm())
 453                 bname = "AM572x EVM";
 454         else if (board_is_am572x_idk())
 455                 bname = "AM572x IDK";
 456         else if (board_is_am571x_idk())
 457                 bname = "AM571x IDK";
 458
 459         if (bname)
 460                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 461                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 462 }
 463
 464 static void setup_board_eeprom_env(void)
 465 {
 466         char *name = "beagle_x15";
 467         int rc;
 468
 469         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 470                                   CONFIG_EEPROM_CHIP_ADDRESS);
 471         if (rc)
 472                 goto invalid_eeprom;
 473
 474         if (board_is_x15()) {
 475                 if (board_is_x15_revb1())
 476                         name = "beagle_x15_revb1";
 477                 else
 478                         name = "beagle_x15";
 479         } else if (board_is_am572x_evm()) {
 480                 if (board_is_am572x_evm_reva3())
 481                         name = "am57xx_evm_reva3";
 482                 else
 483                         name = "am57xx_evm";
 484         } else if (board_is_am572x_idk()) {
 485                 name = "am572x_idk";
 486         } else if (board_is_am571x_idk()) {
 487                 name = "am571x_idk";
 488         } else {
 489                 printf("Unidentified board claims %s in eeprom header\n",
 490                        board_ti_get_name());
 491         }
 492
 493 invalid_eeprom:
 494         set_board_info_env(name);
 495 }
 496
 497 #endif  /* CONFIG_SPL_BUILD */
 498
 499 void vcores_init(void)
 500 {
 501         if (board_is_am572x_idk())
 502                 *omap_vcores = &am572x_idk_volts;
 503         else if (board_is_am571x_idk())
 504                 *omap_vcores = &am571x_idk_volts;
 505         else
 506                 *omap_vcores = &beagle_x15_volts;
 507 }
 508
 509 void hw_data_init(void)
 510 {
 511         *prcm = &dra7xx_prcm;
 512         *dplls_data = &dra7xx_dplls;
 513         *ctrl = &dra7xx_ctrl;
 514 }
 515
 516 bool am571x_idk_needs_lcd(void)
 517 {
 518         bool needs_lcd;
 519
 520         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 521         if (gpio_get_value(GPIO_ETH_LCD))
 522                 needs_lcd = false;
 523         else
 524                 needs_lcd = true;
 525
 526         gpio_free(GPIO_ETH_LCD);
 527
 528         return needs_lcd;
 529 }
 530
 531 int board_init(void)
 532 {
 533         gpmc_init();
 534         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 535
 536         return 0;
 537 }
 538
 539 void am57x_idk_lcd_detect(void)
 540 {
 541         int r = -ENODEV;
 542         char *idk_lcd = "no";
 543         uint8_t buf = 0;
 544
 545         /* Only valid for IDKs */
 546         if (board_is_x15() || board_is_am572x_evm())
 547                 return;
 548
 549         /* Only AM571x IDK has gpio control detect.. so check that */
 550         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 551                 goto out;
 552
 553         r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
 554         if (r) {
 555                 printf("%s: Failed to set bus address to %d: %d\n",
 556                        __func__, OSD_TS_FT_BUS_ADDRESS, r);
 557                 goto out;
 558         }
 559         r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
 560         if (r) {
 561                 /* AM572x IDK has no explicit settings for optional LCD kit */
 562                 if (board_is_am571x_idk()) {
 563                         printf("%s: Touch screen detect failed: %d!\n",
 564                                __func__, r);
 565                 }
 566                 goto out;
 567         }
 568
 569         /* Read FT ID */
 570         r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
 571         if (r) {
 572                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 573                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 574                        OSD_TS_FT_REG_ID, r);
 575                 goto out;
 576         }
 577
 578         switch (buf) {
 579         case OSD_TS_FT_ID_5606:
 580                 idk_lcd = "osd101t2045";
 581                 break;
 582         case OSD_TS_FT_ID_5x46:
 583                 idk_lcd = "osd101t2587";
 584                 break;
 585         default:
 586                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 587                        __func__, buf);
 588                 /* we will let default be "no lcd" */
 589         }
 590 out:
 591         setenv("idk_lcd", idk_lcd);
 592         return;
 593 }
 594
 595 int board_late_init(void)
 596 {
 597         setup_board_eeprom_env();
 598         u8 val;
 599
 600         /*
 601          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 602          * This is the POWERHOLD-in-Low behavior.
 603          */
 604         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 605
 606         /*
 607          * Default FIT boot on HS devices. Non FIT images are not allowed
 608          * on HS devices.
 609          */
 610         if (get_device_type() == HS_DEVICE)
 611                 setenv("boot_fit", "1");
 612
 613         /*
 614          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 615          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 616          * PMIC Power off. So to be on the safer side set it back
 617          * to POWERHOLD mode irrespective of the current state.
 618          */
 619         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 620                            &val);
 621         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 622         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 623                             val);
 624
 625         omap_die_id_serial();
 626
 627         am57x_idk_lcd_detect();
 628
 629 #if !defined(CONFIG_SPL_BUILD)
 630         board_ti_set_ethaddr(2);
 631 #endif
 632
 633         return 0;
 634 }
 635
 636 void set_muxconf_regs(void)
 637 {
 638         do_set_mux32((*ctrl)->control_padconf_core_base,
 639                      early_padconf, ARRAY_SIZE(early_padconf));
 640 }
 641
 642 #ifdef CONFIG_IODELAY_RECALIBRATION
 643 void recalibrate_iodelay(void)
 644 {
 645         const struct pad_conf_entry *pconf;
 646         const struct iodelay_cfg_entry *iod, *delta_iod;
 647         int pconf_sz, iod_sz, delta_iod_sz = 0;
 648         int ret;
 649
 650         if (board_is_am572x_idk()) {
 651                 pconf = core_padconf_array_essential_am572x_idk;
 652                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 653                 iod = iodelay_cfg_array_am572x_idk;
 654                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 655         } else if (board_is_am571x_idk()) {
 656                 pconf = core_padconf_array_essential_am571x_idk;
 657                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 658                 iod = iodelay_cfg_array_am571x_idk;
 659                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 660         } else {
 661                 /* Common for X15/GPEVM */
 662                 pconf = core_padconf_array_essential_x15;
 663                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 664                 /* There never was an SR1.0 X15.. So.. */
 665                 if (omap_revision() == DRA752_ES1_1) {
 666                         iod = iodelay_cfg_array_x15_sr1_1;
 667                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 668                 } else {
 669                         /* Since full production should switch to SR2.0  */
 670                         iod = iodelay_cfg_array_x15_sr2_0;
 671                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 672                 }
 673         }
 674
 675         /* Setup I/O isolation */
 676         ret = __recalibrate_iodelay_start();
 677         if (ret)
 678                 goto err;
 679
 680         /* Do the muxing here */
 681         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 682
 683         /* Now do the weird minor deltas that should be safe */
 684         if (board_is_x15() || board_is_am572x_evm()) {
 685                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) {
 686                         pconf = core_padconf_array_delta_x15_sr2_0;
 687                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 688                 } else {
 689                         pconf = core_padconf_array_delta_x15_sr1_1;
 690                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 691                 }
 692                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 693         }
 694
 695         if (board_is_am571x_idk()) {
 696                 if (am571x_idk_needs_lcd()) {
 697                         pconf = core_padconf_array_vout_am571x_idk;
 698                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 699                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 700                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 701
 702                 } else {
 703                         pconf = core_padconf_array_icss1eth_am571x_idk;
 704                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 705                 }
 706                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 707         }
 708
 709         /* Setup IOdelay configuration */
 710         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 711         if (delta_iod_sz)
 712                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 713                                      delta_iod_sz);
 714
 715 err:
 716         /* Closeup.. remove isolation */
 717         __recalibrate_iodelay_end(ret);
 718 }
 719 #endif
 720
 721 #if defined(CONFIG_MMC)
 722 int board_mmc_init(bd_t *bis)
 723 {
 724         omap_mmc_init(0, 0, 0, -1, -1);
 725         omap_mmc_init(1, 0, 0, -1, -1);
 726         return 0;
 727 }
 728 #endif
 729
 730 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 731 int spl_start_uboot(void)
 732 {
 733         /* break into full u-boot on 'c' */
 734         if (serial_tstc() && serial_getc() == 'c')
 735                 return 1;
 736
 737 #ifdef CONFIG_SPL_ENV_SUPPORT
 738         env_init();
 739         env_relocate_spec();
 740         if (getenv_yesno("boot_os") != 1)
 741                 return 1;
 742 #endif
 743
 744         return 0;
 745 }
 746 #endif
 747
 748 #ifdef CONFIG_USB_DWC3
 749 static struct dwc3_device usb_otg_ss2 = {
 750         .maximum_speed = USB_SPEED_HIGH,
 751         .base = DRA7_USB_OTG_SS2_BASE,
 752         .tx_fifo_resize = false,
 753         .index = 1,
 754 };
 755
 756 static struct dwc3_omap_device usb_otg_ss2_glue = {
 757         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 758         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 759         .index = 1,
 760 };
 761
 762 static struct ti_usb_phy_device usb_phy2_device = {
 763         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 764         .index = 1,
 765 };
 766
 767 int usb_gadget_handle_interrupts(int index)
 768 {
 769         u32 status;
 770
 771         status = dwc3_omap_uboot_interrupt_status(index);
 772         if (status)
 773                 dwc3_uboot_handle_interrupt(index);
 774
 775         return 0;
 776 }
 777 #endif /* CONFIG_USB_DWC3 */
 778
 779 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 780 int omap_xhci_board_usb_init(int index, enum usb_init_type init)
 781 {
 782         enable_usb_clocks(index);
 783         switch (index) {
 784         case 0:
 785                 if (init == USB_INIT_DEVICE) {
 786                         printf("port %d can't be used as device\n", index);
 787                         disable_usb_clocks(index);
 788                         return -EINVAL;
 789                 }
 790                 break;
 791         case 1:
 792                 if (init == USB_INIT_DEVICE) {
 793 #ifdef CONFIG_USB_DWC3
 794                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 795                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 796                         ti_usb_phy_uboot_init(&usb_phy2_device);
 797                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 798                         dwc3_uboot_init(&usb_otg_ss2);
 799 #endif
 800                 } else {
 801                         printf("port %d can't be used as host\n", index);
 802                         disable_usb_clocks(index);
 803                         return -EINVAL;
 804                 }
 805
 806                 break;
 807         default:
 808                 printf("Invalid Controller Index\n");
 809         }
 810
 811         return 0;
 812 }
 813
 814 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
 815 {
 816 #ifdef CONFIG_USB_DWC3
 817         switch (index) {
 818         case 0:
 819         case 1:
 820                 if (init == USB_INIT_DEVICE) {
 821                         ti_usb_phy_uboot_exit(index);
 822                         dwc3_uboot_exit(index);
 823                         dwc3_omap_uboot_exit(index);
 824                 }
 825                 break;
 826         default:
 827                 printf("Invalid Controller Index\n");
 828         }
 829 #endif
 830         disable_usb_clocks(index);
 831         return 0;
 832 }
 833 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 834
 835 #ifdef CONFIG_DRIVER_TI_CPSW
 836
 837 /* Delay value to add to calibrated value */
 838 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 839 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 840 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 841 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 842 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 843 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 844 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 845 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 846 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 847 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 848
 849 static void cpsw_control(int enabled)
 850 {
 851         /* VTP can be added here */
 852 }
 853
 854 static struct cpsw_slave_data cpsw_slaves[] = {
 855         {
 856                 .slave_reg_ofs  = 0x208,
 857                 .sliver_reg_ofs = 0xd80,
 858                 .phy_addr       = 1,
 859         },
 860         {
 861                 .slave_reg_ofs  = 0x308,
 862                 .sliver_reg_ofs = 0xdc0,
 863                 .phy_addr       = 2,
 864         },
 865 };
 866
 867 static struct cpsw_platform_data cpsw_data = {
 868         .mdio_base              = CPSW_MDIO_BASE,
 869         .cpsw_base              = CPSW_BASE,
 870         .mdio_div               = 0xff,
 871         .channels               = 8,
 872         .cpdma_reg_ofs          = 0x800,
 873         .slaves                 = 1,
 874         .slave_data             = cpsw_slaves,
 875         .ale_reg_ofs            = 0xd00,
 876         .ale_entries            = 1024,
 877         .host_port_reg_ofs      = 0x108,
 878         .hw_stats_reg_ofs       = 0x900,
 879         .bd_ram_ofs             = 0x2000,
 880         .mac_control            = (1 << 5),
 881         .control                = cpsw_control,
 882         .host_port_num          = 0,
 883         .version                = CPSW_CTRL_VERSION_2,
 884 };
 885
 886 static u64 mac_to_u64(u8 mac[6])
 887 {
 888         int i;
 889         u64 addr = 0;
 890
 891         for (i = 0; i < 6; i++) {
 892                 addr <<= 8;
 893                 addr |= mac[i];
 894         }
 895
 896         return addr;
 897 }
 898
 899 static void u64_to_mac(u64 addr, u8 mac[6])
 900 {
 901         mac[5] = addr;
 902         mac[4] = addr >> 8;
 903         mac[3] = addr >> 16;
 904         mac[2] = addr >> 24;
 905         mac[1] = addr >> 32;
 906         mac[0] = addr >> 40;
 907 }
 908
 909 int board_eth_init(bd_t *bis)
 910 {
 911         int ret;
 912         uint8_t mac_addr[6];
 913         uint32_t mac_hi, mac_lo;
 914         uint32_t ctrl_val;
 915         int i;
 916         u64 mac1, mac2;
 917         u8 mac_addr1[6], mac_addr2[6];
 918         int num_macs;
 919
 920         /* try reading mac address from efuse */
 921         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 922         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 923         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 924         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 925         mac_addr[2] = mac_hi & 0xFF;
 926         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 927         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 928         mac_addr[5] = mac_lo & 0xFF;
 929
 930         if (!getenv("ethaddr")) {
 931                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 932
 933                 if (is_valid_ethaddr(mac_addr))
 934                         eth_setenv_enetaddr("ethaddr", mac_addr);
 935         }
 936
 937         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 938         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 939         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 940         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 941         mac_addr[2] = mac_hi & 0xFF;
 942         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 943         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 944         mac_addr[5] = mac_lo & 0xFF;
 945
 946         if (!getenv("eth1addr")) {
 947                 if (is_valid_ethaddr(mac_addr))
 948                         eth_setenv_enetaddr("eth1addr", mac_addr);
 949         }
 950
 951         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 952         ctrl_val |= 0x22;
 953         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 954
 955         /* The phy address for the AM57xx IDK are different than x15 */
 956         if (board_is_am572x_idk() || board_is_am571x_idk()) {
 957                 cpsw_data.slave_data[0].phy_addr = 0;
 958                 cpsw_data.slave_data[1].phy_addr = 1;
 959         }
 960
 961         ret = cpsw_register(&cpsw_data);
 962         if (ret < 0)
 963                 printf("Error %d registering CPSW switch\n", ret);
 964
 965         /*
 966          * Export any Ethernet MAC addresses from EEPROM.
 967          * On AM57xx the 2 MAC addresses define the address range
 968          */
 969         board_ti_get_eth_mac_addr(0, mac_addr1);
 970         board_ti_get_eth_mac_addr(1, mac_addr2);
 971
 972         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 973                 mac1 = mac_to_u64(mac_addr1);
 974                 mac2 = mac_to_u64(mac_addr2);
 975
 976                 /* must contain an address range */
 977                 num_macs = mac2 - mac1 + 1;
 978                 /* <= 50 to protect against user programming error */
 979                 if (num_macs > 0 && num_macs <= 50) {
 980                         for (i = 0; i < num_macs; i++) {
 981                                 u64_to_mac(mac1 + i, mac_addr);
 982                                 if (is_valid_ethaddr(mac_addr)) {
 983                                         eth_setenv_enetaddr_by_index("eth",
 984                                                                      i + 2,
 985                                                                      mac_addr);
 986                                 }
 987                         }
 988                 }
 989         }
 990
 991         return ret;
 992 }
 993 #endif
 994
 995 #ifdef CONFIG_BOARD_EARLY_INIT_F
 996 /* VTT regulator enable */
 997 static inline void vtt_regulator_enable(void)
 998 {
 999         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1000                 return;
1001
1002         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1003         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1004 }
1005
1006 int board_early_init_f(void)
1007 {
1008         vtt_regulator_enable();
1009         return 0;
1010 }
1011 #endif
1012
1013 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1014 int ft_board_setup(void *blob, bd_t *bd)
1015 {
1016         ft_cpu_setup(blob, bd);
1017
1018         return 0;
1019 }
1020 #endif
1021
1022 #ifdef CONFIG_SPL_LOAD_FIT
1023 int board_fit_config_name_match(const char *name)
1024 {
1025         if (board_is_x15()) {
1026                 if (board_is_x15_revb1()) {
1027                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1028                                 return 0;
1029                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1030                         return 0;
1031                 }
1032         } else if (board_is_am572x_evm() &&
1033                    !strcmp(name, "am57xx-beagle-x15")) {
1034                 return 0;
1035         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1036                 return 0;
1037         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1038                 return 0;
1039         }
1040
1041         return -1;
1042 }
1043 #endif
1044
1045 #ifdef CONFIG_TI_SECURE_DEVICE
1046 void board_fit_image_post_process(void **p_image, size_t *p_size)
1047 {
1048         secure_boot_verify_image(p_image, p_size);
1049 }
1050
1051 void board_tee_image_process(ulong tee_image, size_t tee_size)
1052 {
1053         secure_tee_install((u32)tee_image);
1054 }
1055
1056 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1057 #endif