git.sur5r.net Git - u-boot/blob - board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  !strncmp("B.10", board_ti_get_rev(), 3))
  40 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  41                                  !strncmp("C.00", board_ti_get_rev(), 3))
  42 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  43 #define board_is_am572x_evm_reva3()     \
  44                                 (board_ti_is("AM572PM_") && \
  45                                  !strncmp("A.30", board_ti_get_rev(), 3))
  46 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  47 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  48
  49 #ifdef CONFIG_DRIVER_TI_CPSW
  50 #include <cpsw.h>
  51 #endif
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  56 /* GPIO 7_11 */
  57 #define GPIO_DDR_VTT_EN 203
  58
  59 /* Touch screen controller to identify the LCD */
  60 #define OSD_TS_FT_BUS_ADDRESS   0
  61 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  62 #define OSD_TS_FT_REG_ID        0xA3
  63 /*
  64  * Touchscreen IDs for various OSD panels
  65  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  66  */
  67 /* Used on newer osd101t2587 Panels */
  68 #define OSD_TS_FT_ID_5x46       0x54
  69 /* Used on older osd101t2045 Panels */
  70 #define OSD_TS_FT_ID_5606       0x08
  71
  72 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  73
  74 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  75 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  76
  77 const struct omap_sysinfo sysinfo = {
  78         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  79 };
  80
  81 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  82         .dmm_lisa_map_3 = 0x80740300,
  83         .is_ma_present  = 0x1
  84 };
  85
  86 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  87         .dmm_lisa_map_3 = 0x80640100,
  88         .is_ma_present  = 0x1
  89 };
  90
  91 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  92 {
  93         if (board_is_am571x_idk())
  94                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
  95         else
  96                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
  97 }
  98
  99 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 100         .sdram_config_init              = 0x61851b32,
 101         .sdram_config                   = 0x61851b32,
 102         .sdram_config2                  = 0x08000000,
 103         .ref_ctrl                       = 0x000040F1,
 104         .ref_ctrl_final                 = 0x00001035,
 105         .sdram_tim1                     = 0xcccf36ab,
 106         .sdram_tim2                     = 0x308f7fda,
 107         .sdram_tim3                     = 0x409f88a8,
 108         .read_idle_ctrl                 = 0x00050000,
 109         .zq_config                      = 0x5007190b,
 110         .temp_alert_config              = 0x00000000,
 111         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 112         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 113         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 114         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 115         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 116         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 117         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 118         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 119         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 120         .emif_rd_wr_lvl_ctl             = 0x00000000,
 121         .emif_rd_wr_exec_thresh         = 0x00000305
 122 };
 123
 124 /* Ext phy ctrl regs 1-35 */
 125 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 126         0x10040100,
 127         0x00910091,
 128         0x00950095,
 129         0x009B009B,
 130         0x009E009E,
 131         0x00980098,
 132         0x00340034,
 133         0x00350035,
 134         0x00340034,
 135         0x00310031,
 136         0x00340034,
 137         0x007F007F,
 138         0x007F007F,
 139         0x007F007F,
 140         0x007F007F,
 141         0x007F007F,
 142         0x00480048,
 143         0x004A004A,
 144         0x00520052,
 145         0x00550055,
 146         0x00500050,
 147         0x00000000,
 148         0x00600020,
 149         0x40011080,
 150         0x08102040,
 151         0x0,
 152         0x0,
 153         0x0,
 154         0x0,
 155         0x0,
 156         0x0,
 157         0x0,
 158         0x0,
 159         0x0,
 160         0x0
 161 };
 162
 163 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 164         .sdram_config_init              = 0x61851b32,
 165         .sdram_config                   = 0x61851b32,
 166         .sdram_config2                  = 0x08000000,
 167         .ref_ctrl                       = 0x000040F1,
 168         .ref_ctrl_final                 = 0x00001035,
 169         .sdram_tim1                     = 0xcccf36b3,
 170         .sdram_tim2                     = 0x308f7fda,
 171         .sdram_tim3                     = 0x407f88a8,
 172         .read_idle_ctrl                 = 0x00050000,
 173         .zq_config                      = 0x5007190b,
 174         .temp_alert_config              = 0x00000000,
 175         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 176         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 177         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 178         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 179         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 180         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 181         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 182         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 183         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 184         .emif_rd_wr_lvl_ctl             = 0x00000000,
 185         .emif_rd_wr_exec_thresh         = 0x00000305
 186 };
 187
 188 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 189         0x10040100,
 190         0x00910091,
 191         0x00950095,
 192         0x009B009B,
 193         0x009E009E,
 194         0x00980098,
 195         0x00340034,
 196         0x00350035,
 197         0x00340034,
 198         0x00310031,
 199         0x00340034,
 200         0x007F007F,
 201         0x007F007F,
 202         0x007F007F,
 203         0x007F007F,
 204         0x007F007F,
 205         0x00480048,
 206         0x004A004A,
 207         0x00520052,
 208         0x00550055,
 209         0x00500050,
 210         0x00000000,
 211         0x00600020,
 212         0x40011080,
 213         0x08102040,
 214         0x0,
 215         0x0,
 216         0x0,
 217         0x0,
 218         0x0,
 219         0x0,
 220         0x0,
 221         0x0,
 222         0x0,
 223         0x0
 224 };
 225
 226 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 227         .sdram_config_init              = 0x61863332,
 228         .sdram_config                   = 0x61863332,
 229         .sdram_config2                  = 0x08000000,
 230         .ref_ctrl                       = 0x0000514d,
 231         .ref_ctrl_final                 = 0x0000144a,
 232         .sdram_tim1                     = 0xd333887c,
 233         .sdram_tim2                     = 0x40b37fe3,
 234         .sdram_tim3                     = 0x409f8ada,
 235         .read_idle_ctrl                 = 0x00050000,
 236         .zq_config                      = 0x5007190b,
 237         .temp_alert_config              = 0x00000000,
 238         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 239         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 240         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 241         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 242         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 243         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 244         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 245         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 246         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 247         .emif_rd_wr_lvl_ctl             = 0x00000000,
 248         .emif_rd_wr_exec_thresh         = 0x00000305
 249 };
 250
 251 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 252 {
 253         switch (emif_nr) {
 254         case 1:
 255                 if (board_is_am571x_idk())
 256                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 257                 else
 258                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 259                 break;
 260         case 2:
 261                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 262                 break;
 263         }
 264 }
 265
 266 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 267 {
 268         switch (emif_nr) {
 269         case 1:
 270                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 271                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 272                 break;
 273         case 2:
 274                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 275                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 276                 break;
 277         }
 278 }
 279
 280 struct vcores_data beagle_x15_volts = {
 281         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 282         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 283         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 284         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 285         .mpu.pmic               = &tps659038,
 286         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 287
 288         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 289         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 290         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 291         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 292         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 293         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 294         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 295         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 296         .eve.pmic               = &tps659038,
 297         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 298
 299         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 300         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 301         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 302         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 303         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 304         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 305         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 306         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 307         .gpu.pmic               = &tps659038,
 308         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 309
 310         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 311         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 312         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 313         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 314         .core.pmic              = &tps659038,
 315
 316         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 317         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 318         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 319         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 320         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 321         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 322         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 323         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 324         .iva.pmic               = &tps659038,
 325         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 326 };
 327
 328 struct vcores_data am572x_idk_volts = {
 329         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 330         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 331         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 332         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 333         .mpu.pmic               = &tps659038,
 334         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 335
 336         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 337         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 338         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 339         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 340         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 341         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 342         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 343         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 344         .eve.pmic               = &tps659038,
 345         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 346
 347         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 348         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 349         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 350         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 351         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 352         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 353         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 354         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 355         .gpu.pmic               = &tps659038,
 356         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 357
 358         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 359         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 360         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 361         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 362         .core.pmic              = &tps659038,
 363
 364         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 365         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 366         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 367         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 368         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 369         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 370         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 371         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 372         .iva.pmic               = &tps659038,
 373         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 374 };
 375
 376 struct vcores_data am571x_idk_volts = {
 377         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 378         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 379         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 380         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 381         .mpu.pmic               = &tps659038,
 382         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 383
 384         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 385         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 386         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 387         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 388         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 389         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 390         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 391         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 392         .eve.pmic               = &tps659038,
 393         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 394
 395         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 396         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 397         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 398         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 399         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 400         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 401         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 402         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 403         .gpu.pmic               = &tps659038,
 404         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 405
 406         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 407         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 408         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 409         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 410         .core.pmic              = &tps659038,
 411
 412         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 413         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 414         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 415         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 416         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 417         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 418         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 419         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 420         .iva.pmic               = &tps659038,
 421         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 422 };
 423
 424 int get_voltrail_opp(int rail_offset)
 425 {
 426         int opp;
 427
 428         switch (rail_offset) {
 429         case VOLT_MPU:
 430                 opp = DRA7_MPU_OPP;
 431                 break;
 432         case VOLT_CORE:
 433                 opp = DRA7_CORE_OPP;
 434                 break;
 435         case VOLT_GPU:
 436                 opp = DRA7_GPU_OPP;
 437                 break;
 438         case VOLT_EVE:
 439                 opp = DRA7_DSPEVE_OPP;
 440                 break;
 441         case VOLT_IVA:
 442                 opp = DRA7_IVA_OPP;
 443                 break;
 444         default:
 445                 opp = OPP_NOM;
 446         }
 447
 448         return opp;
 449 }
 450
 451
 452 #ifdef CONFIG_SPL_BUILD
 453 /* No env to setup for SPL */
 454 static inline void setup_board_eeprom_env(void) { }
 455
 456 /* Override function to read eeprom information */
 457 void do_board_detect(void)
 458 {
 459         int rc;
 460
 461         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 462                                   CONFIG_EEPROM_CHIP_ADDRESS);
 463         if (rc)
 464                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 465 }
 466
 467 #else   /* CONFIG_SPL_BUILD */
 468
 469 /* Override function to read eeprom information: actual i2c read done by SPL*/
 470 void do_board_detect(void)
 471 {
 472         char *bname = NULL;
 473         int rc;
 474
 475         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 476                                   CONFIG_EEPROM_CHIP_ADDRESS);
 477         if (rc)
 478                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 479
 480         if (board_is_x15())
 481                 bname = "BeagleBoard X15";
 482         else if (board_is_am572x_evm())
 483                 bname = "AM572x EVM";
 484         else if (board_is_am572x_idk())
 485                 bname = "AM572x IDK";
 486         else if (board_is_am571x_idk())
 487                 bname = "AM571x IDK";
 488
 489         if (bname)
 490                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 491                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 492 }
 493
 494 static void setup_board_eeprom_env(void)
 495 {
 496         char *name = "beagle_x15";
 497         int rc;
 498
 499         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 500                                   CONFIG_EEPROM_CHIP_ADDRESS);
 501         if (rc)
 502                 goto invalid_eeprom;
 503
 504         if (board_is_x15()) {
 505                 if (board_is_x15_revb1())
 506                         name = "beagle_x15_revb1";
 507                 else if (board_is_x15_revc())
 508                         name = "beagle_x15_revc";
 509                 else
 510                         name = "beagle_x15";
 511         } else if (board_is_am572x_evm()) {
 512                 if (board_is_am572x_evm_reva3())
 513                         name = "am57xx_evm_reva3";
 514                 else
 515                         name = "am57xx_evm";
 516         } else if (board_is_am572x_idk()) {
 517                 name = "am572x_idk";
 518         } else if (board_is_am571x_idk()) {
 519                 name = "am571x_idk";
 520         } else {
 521                 printf("Unidentified board claims %s in eeprom header\n",
 522                        board_ti_get_name());
 523         }
 524
 525 invalid_eeprom:
 526         set_board_info_env(name);
 527 }
 528
 529 #endif  /* CONFIG_SPL_BUILD */
 530
 531 void vcores_init(void)
 532 {
 533         if (board_is_am572x_idk())
 534                 *omap_vcores = &am572x_idk_volts;
 535         else if (board_is_am571x_idk())
 536                 *omap_vcores = &am571x_idk_volts;
 537         else
 538                 *omap_vcores = &beagle_x15_volts;
 539 }
 540
 541 void hw_data_init(void)
 542 {
 543         *prcm = &dra7xx_prcm;
 544         if (is_dra72x())
 545                 *dplls_data = &dra72x_dplls;
 546         else
 547                 *dplls_data = &dra7xx_dplls;
 548         *ctrl = &dra7xx_ctrl;
 549 }
 550
 551 bool am571x_idk_needs_lcd(void)
 552 {
 553         bool needs_lcd;
 554
 555         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 556         if (gpio_get_value(GPIO_ETH_LCD))
 557                 needs_lcd = false;
 558         else
 559                 needs_lcd = true;
 560
 561         gpio_free(GPIO_ETH_LCD);
 562
 563         return needs_lcd;
 564 }
 565
 566 int board_init(void)
 567 {
 568         gpmc_init();
 569         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 570
 571         return 0;
 572 }
 573
 574 void am57x_idk_lcd_detect(void)
 575 {
 576         int r = -ENODEV;
 577         char *idk_lcd = "no";
 578         uint8_t buf = 0;
 579
 580         /* Only valid for IDKs */
 581         if (board_is_x15() || board_is_am572x_evm())
 582                 return;
 583
 584         /* Only AM571x IDK has gpio control detect.. so check that */
 585         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 586                 goto out;
 587
 588         r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
 589         if (r) {
 590                 printf("%s: Failed to set bus address to %d: %d\n",
 591                        __func__, OSD_TS_FT_BUS_ADDRESS, r);
 592                 goto out;
 593         }
 594         r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
 595         if (r) {
 596                 /* AM572x IDK has no explicit settings for optional LCD kit */
 597                 if (board_is_am571x_idk()) {
 598                         printf("%s: Touch screen detect failed: %d!\n",
 599                                __func__, r);
 600                 }
 601                 goto out;
 602         }
 603
 604         /* Read FT ID */
 605         r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
 606         if (r) {
 607                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 608                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 609                        OSD_TS_FT_REG_ID, r);
 610                 goto out;
 611         }
 612
 613         switch (buf) {
 614         case OSD_TS_FT_ID_5606:
 615                 idk_lcd = "osd101t2045";
 616                 break;
 617         case OSD_TS_FT_ID_5x46:
 618                 idk_lcd = "osd101t2587";
 619                 break;
 620         default:
 621                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 622                        __func__, buf);
 623                 /* we will let default be "no lcd" */
 624         }
 625 out:
 626         env_set("idk_lcd", idk_lcd);
 627         return;
 628 }
 629
 630 int board_late_init(void)
 631 {
 632         setup_board_eeprom_env();
 633         u8 val;
 634
 635         /*
 636          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 637          * This is the POWERHOLD-in-Low behavior.
 638          */
 639         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 640
 641         /*
 642          * Default FIT boot on HS devices. Non FIT images are not allowed
 643          * on HS devices.
 644          */
 645         if (get_device_type() == HS_DEVICE)
 646                 env_set("boot_fit", "1");
 647
 648         /*
 649          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 650          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 651          * PMIC Power off. So to be on the safer side set it back
 652          * to POWERHOLD mode irrespective of the current state.
 653          */
 654         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 655                            &val);
 656         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 657         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 658                             val);
 659
 660         omap_die_id_serial();
 661         omap_set_fastboot_vars();
 662
 663         am57x_idk_lcd_detect();
 664
 665 #if !defined(CONFIG_SPL_BUILD)
 666         board_ti_set_ethaddr(2);
 667 #endif
 668
 669         return 0;
 670 }
 671
 672 void set_muxconf_regs(void)
 673 {
 674         do_set_mux32((*ctrl)->control_padconf_core_base,
 675                      early_padconf, ARRAY_SIZE(early_padconf));
 676 }
 677
 678 #ifdef CONFIG_IODELAY_RECALIBRATION
 679 void recalibrate_iodelay(void)
 680 {
 681         const struct pad_conf_entry *pconf;
 682         const struct iodelay_cfg_entry *iod, *delta_iod;
 683         int pconf_sz, iod_sz, delta_iod_sz = 0;
 684         int ret;
 685
 686         if (board_is_am572x_idk()) {
 687                 pconf = core_padconf_array_essential_am572x_idk;
 688                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 689                 iod = iodelay_cfg_array_am572x_idk;
 690                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 691         } else if (board_is_am571x_idk()) {
 692                 pconf = core_padconf_array_essential_am571x_idk;
 693                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 694                 iod = iodelay_cfg_array_am571x_idk;
 695                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 696         } else {
 697                 /* Common for X15/GPEVM */
 698                 pconf = core_padconf_array_essential_x15;
 699                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 700                 /* There never was an SR1.0 X15.. So.. */
 701                 if (omap_revision() == DRA752_ES1_1) {
 702                         iod = iodelay_cfg_array_x15_sr1_1;
 703                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 704                 } else {
 705                         /* Since full production should switch to SR2.0  */
 706                         iod = iodelay_cfg_array_x15_sr2_0;
 707                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 708                 }
 709         }
 710
 711         /* Setup I/O isolation */
 712         ret = __recalibrate_iodelay_start();
 713         if (ret)
 714                 goto err;
 715
 716         /* Do the muxing here */
 717         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 718
 719         /* Now do the weird minor deltas that should be safe */
 720         if (board_is_x15() || board_is_am572x_evm()) {
 721                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 722                     board_is_x15_revc()) {
 723                         pconf = core_padconf_array_delta_x15_sr2_0;
 724                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 725                 } else {
 726                         pconf = core_padconf_array_delta_x15_sr1_1;
 727                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 728                 }
 729                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 730         }
 731
 732         if (board_is_am571x_idk()) {
 733                 if (am571x_idk_needs_lcd()) {
 734                         pconf = core_padconf_array_vout_am571x_idk;
 735                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 736                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 737                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 738
 739                 } else {
 740                         pconf = core_padconf_array_icss1eth_am571x_idk;
 741                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 742                 }
 743                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 744         }
 745
 746         /* Setup IOdelay configuration */
 747         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 748         if (delta_iod_sz)
 749                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 750                                      delta_iod_sz);
 751
 752 err:
 753         /* Closeup.. remove isolation */
 754         __recalibrate_iodelay_end(ret);
 755 }
 756 #endif
 757
 758 #if defined(CONFIG_MMC)
 759 int board_mmc_init(bd_t *bis)
 760 {
 761         omap_mmc_init(0, 0, 0, -1, -1);
 762         omap_mmc_init(1, 0, 0, -1, -1);
 763         return 0;
 764 }
 765 #endif
 766
 767 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 768 int spl_start_uboot(void)
 769 {
 770         /* break into full u-boot on 'c' */
 771         if (serial_tstc() && serial_getc() == 'c')
 772                 return 1;
 773
 774 #ifdef CONFIG_SPL_ENV_SUPPORT
 775         env_init();
 776         env_load();
 777         if (env_get_yesno("boot_os") != 1)
 778                 return 1;
 779 #endif
 780
 781         return 0;
 782 }
 783 #endif
 784
 785 #ifdef CONFIG_USB_DWC3
 786 static struct dwc3_device usb_otg_ss2 = {
 787         .maximum_speed = USB_SPEED_HIGH,
 788         .base = DRA7_USB_OTG_SS2_BASE,
 789         .tx_fifo_resize = false,
 790         .index = 1,
 791 };
 792
 793 static struct dwc3_omap_device usb_otg_ss2_glue = {
 794         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 795         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 796         .index = 1,
 797 };
 798
 799 static struct ti_usb_phy_device usb_phy2_device = {
 800         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 801         .index = 1,
 802 };
 803
 804 int usb_gadget_handle_interrupts(int index)
 805 {
 806         u32 status;
 807
 808         status = dwc3_omap_uboot_interrupt_status(index);
 809         if (status)
 810                 dwc3_uboot_handle_interrupt(index);
 811
 812         return 0;
 813 }
 814 #endif /* CONFIG_USB_DWC3 */
 815
 816 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 817 int omap_xhci_board_usb_init(int index, enum usb_init_type init)
 818 {
 819         enable_usb_clocks(index);
 820         switch (index) {
 821         case 0:
 822                 if (init == USB_INIT_DEVICE) {
 823                         printf("port %d can't be used as device\n", index);
 824                         disable_usb_clocks(index);
 825                         return -EINVAL;
 826                 }
 827                 break;
 828         case 1:
 829                 if (init == USB_INIT_DEVICE) {
 830 #ifdef CONFIG_USB_DWC3
 831                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 832                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 833                         ti_usb_phy_uboot_init(&usb_phy2_device);
 834                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 835                         dwc3_uboot_init(&usb_otg_ss2);
 836 #endif
 837                 } else {
 838                         printf("port %d can't be used as host\n", index);
 839                         disable_usb_clocks(index);
 840                         return -EINVAL;
 841                 }
 842
 843                 break;
 844         default:
 845                 printf("Invalid Controller Index\n");
 846         }
 847
 848         return 0;
 849 }
 850
 851 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
 852 {
 853 #ifdef CONFIG_USB_DWC3
 854         switch (index) {
 855         case 0:
 856         case 1:
 857                 if (init == USB_INIT_DEVICE) {
 858                         ti_usb_phy_uboot_exit(index);
 859                         dwc3_uboot_exit(index);
 860                         dwc3_omap_uboot_exit(index);
 861                 }
 862                 break;
 863         default:
 864                 printf("Invalid Controller Index\n");
 865         }
 866 #endif
 867         disable_usb_clocks(index);
 868         return 0;
 869 }
 870 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 871
 872 #ifdef CONFIG_DRIVER_TI_CPSW
 873
 874 /* Delay value to add to calibrated value */
 875 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 876 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 877 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 878 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 879 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 880 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 881 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 882 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 883 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 884 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 885
 886 static void cpsw_control(int enabled)
 887 {
 888         /* VTP can be added here */
 889 }
 890
 891 static struct cpsw_slave_data cpsw_slaves[] = {
 892         {
 893                 .slave_reg_ofs  = 0x208,
 894                 .sliver_reg_ofs = 0xd80,
 895                 .phy_addr       = 1,
 896         },
 897         {
 898                 .slave_reg_ofs  = 0x308,
 899                 .sliver_reg_ofs = 0xdc0,
 900                 .phy_addr       = 2,
 901         },
 902 };
 903
 904 static struct cpsw_platform_data cpsw_data = {
 905         .mdio_base              = CPSW_MDIO_BASE,
 906         .cpsw_base              = CPSW_BASE,
 907         .mdio_div               = 0xff,
 908         .channels               = 8,
 909         .cpdma_reg_ofs          = 0x800,
 910         .slaves                 = 1,
 911         .slave_data             = cpsw_slaves,
 912         .ale_reg_ofs            = 0xd00,
 913         .ale_entries            = 1024,
 914         .host_port_reg_ofs      = 0x108,
 915         .hw_stats_reg_ofs       = 0x900,
 916         .bd_ram_ofs             = 0x2000,
 917         .mac_control            = (1 << 5),
 918         .control                = cpsw_control,
 919         .host_port_num          = 0,
 920         .version                = CPSW_CTRL_VERSION_2,
 921 };
 922
 923 static u64 mac_to_u64(u8 mac[6])
 924 {
 925         int i;
 926         u64 addr = 0;
 927
 928         for (i = 0; i < 6; i++) {
 929                 addr <<= 8;
 930                 addr |= mac[i];
 931         }
 932
 933         return addr;
 934 }
 935
 936 static void u64_to_mac(u64 addr, u8 mac[6])
 937 {
 938         mac[5] = addr;
 939         mac[4] = addr >> 8;
 940         mac[3] = addr >> 16;
 941         mac[2] = addr >> 24;
 942         mac[1] = addr >> 32;
 943         mac[0] = addr >> 40;
 944 }
 945
 946 int board_eth_init(bd_t *bis)
 947 {
 948         int ret;
 949         uint8_t mac_addr[6];
 950         uint32_t mac_hi, mac_lo;
 951         uint32_t ctrl_val;
 952         int i;
 953         u64 mac1, mac2;
 954         u8 mac_addr1[6], mac_addr2[6];
 955         int num_macs;
 956
 957         /* try reading mac address from efuse */
 958         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 959         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 960         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 961         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 962         mac_addr[2] = mac_hi & 0xFF;
 963         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 964         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 965         mac_addr[5] = mac_lo & 0xFF;
 966
 967         if (!env_get("ethaddr")) {
 968                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 969
 970                 if (is_valid_ethaddr(mac_addr))
 971                         eth_env_set_enetaddr("ethaddr", mac_addr);
 972         }
 973
 974         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 975         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 976         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 977         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 978         mac_addr[2] = mac_hi & 0xFF;
 979         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 980         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 981         mac_addr[5] = mac_lo & 0xFF;
 982
 983         if (!env_get("eth1addr")) {
 984                 if (is_valid_ethaddr(mac_addr))
 985                         eth_env_set_enetaddr("eth1addr", mac_addr);
 986         }
 987
 988         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 989         ctrl_val |= 0x22;
 990         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 991
 992         /* The phy address for the AM57xx IDK are different than x15 */
 993         if (board_is_am572x_idk() || board_is_am571x_idk()) {
 994                 cpsw_data.slave_data[0].phy_addr = 0;
 995                 cpsw_data.slave_data[1].phy_addr = 1;
 996         }
 997
 998         ret = cpsw_register(&cpsw_data);
 999         if (ret < 0)
1000                 printf("Error %d registering CPSW switch\n", ret);
1001
1002         /*
1003          * Export any Ethernet MAC addresses from EEPROM.
1004          * On AM57xx the 2 MAC addresses define the address range
1005          */
1006         board_ti_get_eth_mac_addr(0, mac_addr1);
1007         board_ti_get_eth_mac_addr(1, mac_addr2);
1008
1009         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1010                 mac1 = mac_to_u64(mac_addr1);
1011                 mac2 = mac_to_u64(mac_addr2);
1012
1013                 /* must contain an address range */
1014                 num_macs = mac2 - mac1 + 1;
1015                 /* <= 50 to protect against user programming error */
1016                 if (num_macs > 0 && num_macs <= 50) {
1017                         for (i = 0; i < num_macs; i++) {
1018                                 u64_to_mac(mac1 + i, mac_addr);
1019                                 if (is_valid_ethaddr(mac_addr)) {
1020                                         eth_env_set_enetaddr_by_index("eth",
1021                                                                       i + 2,
1022                                                                       mac_addr);
1023                                 }
1024                         }
1025                 }
1026         }
1027
1028         return ret;
1029 }
1030 #endif
1031
1032 #ifdef CONFIG_BOARD_EARLY_INIT_F
1033 /* VTT regulator enable */
1034 static inline void vtt_regulator_enable(void)
1035 {
1036         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1037                 return;
1038
1039         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1040         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1041 }
1042
1043 int board_early_init_f(void)
1044 {
1045         vtt_regulator_enable();
1046         return 0;
1047 }
1048 #endif
1049
1050 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1051 int ft_board_setup(void *blob, bd_t *bd)
1052 {
1053         ft_cpu_setup(blob, bd);
1054
1055         return 0;
1056 }
1057 #endif
1058
1059 #ifdef CONFIG_SPL_LOAD_FIT
1060 int board_fit_config_name_match(const char *name)
1061 {
1062         if (board_is_x15()) {
1063                 if (board_is_x15_revb1()) {
1064                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1065                                 return 0;
1066                 } else if (board_is_x15_revc()) {
1067                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1068                                 return 0;
1069                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1070                         return 0;
1071                 }
1072         } else if (board_is_am572x_evm() &&
1073                    !strcmp(name, "am57xx-beagle-x15")) {
1074                 return 0;
1075         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1076                 return 0;
1077         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1078                 return 0;
1079         }
1080
1081         return -1;
1082 }
1083 #endif
1084
1085 #ifdef CONFIG_TI_SECURE_DEVICE
1086 void board_fit_image_post_process(void **p_image, size_t *p_size)
1087 {
1088         secure_boot_verify_image(p_image, p_size);
1089 }
1090
1091 void board_tee_image_process(ulong tee_image, size_t tee_size)
1092 {
1093         secure_tee_install((u32)tee_image);
1094 }
1095
1096 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1097 #endif