git.sur5r.net Git - u-boot/blob - board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/omap.h>
  26 #include <environment.h>
  27 #include <usb.h>
  28 #include <linux/usb/gadget.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32
  33 #include "../common/board_detect.h"
  34 #include "mux_data.h"
  35
  36 #define board_is_x15()          board_ti_is("BBRDX15_")
  37 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  38 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  39
  40 #ifdef CONFIG_DRIVER_TI_CPSW
  41 #include <cpsw.h>
  42 #endif
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO 7_11 */
  47 #define GPIO_DDR_VTT_EN 203
  48
  49 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  50
  51 const struct omap_sysinfo sysinfo = {
  52         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  53 };
  54
  55 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  56         .dmm_lisa_map_3 = 0x80740300,
  57         .is_ma_present  = 0x1
  58 };
  59
  60 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  61 {
  62         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  63 }
  64
  65 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  66         .sdram_config_init      = 0x61851b32,
  67         .sdram_config           = 0x61851b32,
  68         .sdram_config2          = 0x08000000,
  69         .ref_ctrl               = 0x000040F1,
  70         .ref_ctrl_final         = 0x00001035,
  71         .sdram_tim1             = 0xcccf36ab,
  72         .sdram_tim2             = 0x308f7fda,
  73         .sdram_tim3             = 0x409f88a8,
  74         .read_idle_ctrl         = 0x00050000,
  75         .zq_config              = 0x5007190b,
  76         .temp_alert_config      = 0x00000000,
  77         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  78         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
  79         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  80         .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  81         .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  82         .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  83         .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  84         .emif_rd_wr_lvl_rmp_win = 0x00000000,
  85         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  86         .emif_rd_wr_lvl_ctl     = 0x00000000,
  87         .emif_rd_wr_exec_thresh = 0x00000305
  88 };
  89
  90 /* Ext phy ctrl regs 1-35 */
  91 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  92         0x10040100,
  93         0x00910091,
  94         0x00950095,
  95         0x009B009B,
  96         0x009E009E,
  97         0x00980098,
  98         0x00340034,
  99         0x00350035,
 100         0x00340034,
 101         0x00310031,
 102         0x00340034,
 103         0x007F007F,
 104         0x007F007F,
 105         0x007F007F,
 106         0x007F007F,
 107         0x007F007F,
 108         0x00480048,
 109         0x004A004A,
 110         0x00520052,
 111         0x00550055,
 112         0x00500050,
 113         0x00000000,
 114         0x00600020,
 115         0x40011080,
 116         0x08102040,
 117         0x0,
 118         0x0,
 119         0x0,
 120         0x0,
 121         0x0,
 122         0x0,
 123         0x0,
 124         0x0,
 125         0x0,
 126         0x0
 127 };
 128
 129 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 130         .sdram_config_init      = 0x61851b32,
 131         .sdram_config           = 0x61851b32,
 132         .sdram_config2          = 0x08000000,
 133         .ref_ctrl               = 0x000040F1,
 134         .ref_ctrl_final         = 0x00001035,
 135         .sdram_tim1             = 0xcccf36b3,
 136         .sdram_tim2             = 0x308f7fda,
 137         .sdram_tim3             = 0x407f88a8,
 138         .read_idle_ctrl         = 0x00050000,
 139         .zq_config              = 0x5007190b,
 140         .temp_alert_config      = 0x00000000,
 141         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
 142         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
 143         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
 144         .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
 145         .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
 146         .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
 147         .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
 148         .emif_rd_wr_lvl_rmp_win = 0x00000000,
 149         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
 150         .emif_rd_wr_lvl_ctl     = 0x00000000,
 151         .emif_rd_wr_exec_thresh = 0x00000305
 152 };
 153
 154 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 155         0x10040100,
 156         0x00910091,
 157         0x00950095,
 158         0x009B009B,
 159         0x009E009E,
 160         0x00980098,
 161         0x00340034,
 162         0x00350035,
 163         0x00340034,
 164         0x00310031,
 165         0x00340034,
 166         0x007F007F,
 167         0x007F007F,
 168         0x007F007F,
 169         0x007F007F,
 170         0x007F007F,
 171         0x00480048,
 172         0x004A004A,
 173         0x00520052,
 174         0x00550055,
 175         0x00500050,
 176         0x00000000,
 177         0x00600020,
 178         0x40011080,
 179         0x08102040,
 180         0x0,
 181         0x0,
 182         0x0,
 183         0x0,
 184         0x0,
 185         0x0,
 186         0x0,
 187         0x0,
 188         0x0,
 189         0x0
 190 };
 191
 192 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 193 {
 194         switch (emif_nr) {
 195         case 1:
 196                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 197                 break;
 198         case 2:
 199                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 200                 break;
 201         }
 202 }
 203
 204 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 205 {
 206         switch (emif_nr) {
 207         case 1:
 208                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 209                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 210                 break;
 211         case 2:
 212                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 213                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 214                 break;
 215         }
 216 }
 217
 218 struct vcores_data beagle_x15_volts = {
 219         .mpu.value              = VDD_MPU_DRA752,
 220         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU_NOM,
 221         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 222         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 223         .mpu.pmic               = &tps659038,
 224         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 225
 226         .eve.value              = VDD_EVE_DRA752,
 227         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 228         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 229         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 230         .eve.pmic               = &tps659038,
 231         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 232
 233         .gpu.value              = VDD_GPU_DRA752,
 234         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU_NOM,
 235         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 236         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 237         .gpu.pmic               = &tps659038,
 238         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 239
 240         .core.value             = VDD_CORE_DRA752,
 241         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE_NOM,
 242         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 243         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 244         .core.pmic              = &tps659038,
 245
 246         .iva.value              = VDD_IVA_DRA752,
 247         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA_NOM,
 248         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 249         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 250         .iva.pmic               = &tps659038,
 251         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 252 };
 253
 254 #ifdef CONFIG_SPL_BUILD
 255 /* No env to setup for SPL */
 256 static inline void setup_board_eeprom_env(void) { }
 257
 258 /* Override function to read eeprom information */
 259 void do_board_detect(void)
 260 {
 261         int rc;
 262
 263         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 264                                   CONFIG_EEPROM_CHIP_ADDRESS);
 265         if (rc)
 266                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 267 }
 268
 269 #else   /* CONFIG_SPL_BUILD */
 270
 271 /* Override function to read eeprom information: actual i2c read done by SPL*/
 272 void do_board_detect(void)
 273 {
 274         char *bname = NULL;
 275         int rc;
 276
 277         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 278                                   CONFIG_EEPROM_CHIP_ADDRESS);
 279         if (rc)
 280                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 281
 282         if (board_is_x15())
 283                 bname = "BeagleBoard X15";
 284         else if (board_is_am572x_evm())
 285                 bname = "AM572x EVM";
 286         else if (board_is_am572x_idk())
 287                 bname = "AM572x IDK";
 288
 289         if (bname)
 290                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 291                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 292 }
 293
 294 static void setup_board_eeprom_env(void)
 295 {
 296         char *name = "beagle_x15";
 297         int rc;
 298
 299         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 300                                   CONFIG_EEPROM_CHIP_ADDRESS);
 301         if (rc)
 302                 goto invalid_eeprom;
 303
 304         if (board_is_am572x_evm())
 305                 name = "am57xx_evm";
 306         else if (board_is_am572x_idk())
 307                 name = "am572x_idk";
 308         else
 309                 printf("Unidentified board claims %s in eeprom header\n",
 310                        board_ti_get_name());
 311
 312 invalid_eeprom:
 313         set_board_info_env(name);
 314 }
 315
 316 #endif  /* CONFIG_SPL_BUILD */
 317
 318 void hw_data_init(void)
 319 {
 320         *prcm = &dra7xx_prcm;
 321         *dplls_data = &dra7xx_dplls;
 322         *omap_vcores = &beagle_x15_volts;
 323         *ctrl = &dra7xx_ctrl;
 324 }
 325
 326 int board_init(void)
 327 {
 328         gpmc_init();
 329         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 330
 331         return 0;
 332 }
 333
 334 int board_late_init(void)
 335 {
 336         setup_board_eeprom_env();
 337
 338         /*
 339          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 340          * This is the POWERHOLD-in-Low behavior.
 341          */
 342         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 343         return 0;
 344 }
 345
 346 void set_muxconf_regs(void)
 347 {
 348         do_set_mux32((*ctrl)->control_padconf_core_base,
 349                      early_padconf, ARRAY_SIZE(early_padconf));
 350 }
 351
 352 #ifdef CONFIG_IODELAY_RECALIBRATION
 353 void recalibrate_iodelay(void)
 354 {
 355         const struct pad_conf_entry *pconf;
 356         const struct iodelay_cfg_entry *iod;
 357         int pconf_sz, iod_sz;
 358
 359         if (board_is_am572x_idk()) {
 360                 pconf = core_padconf_array_essential_am572x_idk;
 361                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 362                 iod = iodelay_cfg_array_am572x_idk;
 363                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 364         } else {
 365                 /* Common for X15/GPEVM */
 366                 pconf = core_padconf_array_essential_x15;
 367                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 368                 iod = iodelay_cfg_array_x15;
 369                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
 370         }
 371
 372         __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 373 }
 374 #endif
 375
 376 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 377 int board_mmc_init(bd_t *bis)
 378 {
 379         omap_mmc_init(0, 0, 0, -1, -1);
 380         omap_mmc_init(1, 0, 0, -1, -1);
 381         return 0;
 382 }
 383 #endif
 384
 385 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 386 int spl_start_uboot(void)
 387 {
 388         /* break into full u-boot on 'c' */
 389         if (serial_tstc() && serial_getc() == 'c')
 390                 return 1;
 391
 392 #ifdef CONFIG_SPL_ENV_SUPPORT
 393         env_init();
 394         env_relocate_spec();
 395         if (getenv_yesno("boot_os") != 1)
 396                 return 1;
 397 #endif
 398
 399         return 0;
 400 }
 401 #endif
 402
 403 #ifdef CONFIG_USB_DWC3
 404 static struct dwc3_device usb_otg_ss1 = {
 405         .maximum_speed = USB_SPEED_SUPER,
 406         .base = DRA7_USB_OTG_SS1_BASE,
 407         .tx_fifo_resize = false,
 408         .index = 0,
 409 };
 410
 411 static struct dwc3_omap_device usb_otg_ss1_glue = {
 412         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 413         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 414         .index = 0,
 415 };
 416
 417 static struct ti_usb_phy_device usb_phy1_device = {
 418         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 419         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 420         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 421         .index = 0,
 422 };
 423
 424 static struct dwc3_device usb_otg_ss2 = {
 425         .maximum_speed = USB_SPEED_HIGH,
 426         .base = DRA7_USB_OTG_SS2_BASE,
 427         .tx_fifo_resize = false,
 428         .index = 1,
 429 };
 430
 431 static struct dwc3_omap_device usb_otg_ss2_glue = {
 432         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 433         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 434         .index = 1,
 435 };
 436
 437 static struct ti_usb_phy_device usb_phy2_device = {
 438         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 439         .index = 1,
 440 };
 441
 442 int board_usb_init(int index, enum usb_init_type init)
 443 {
 444         enable_usb_clocks(index);
 445         switch (index) {
 446         case 0:
 447                 if (init == USB_INIT_DEVICE) {
 448                         printf("port %d can't be used as device\n", index);
 449                         disable_usb_clocks(index);
 450                         return -EINVAL;
 451                 } else {
 452                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 453                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 454                         setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 455                                      OTG_SS_CLKCTRL_MODULEMODE_HW |
 456                                      OPTFCLKEN_REFCLK960M);
 457                 }
 458
 459                 ti_usb_phy_uboot_init(&usb_phy1_device);
 460                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 461                 dwc3_uboot_init(&usb_otg_ss1);
 462                 break;
 463         case 1:
 464                 if (init == USB_INIT_DEVICE) {
 465                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 466                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 467                 } else {
 468                         printf("port %d can't be used as host\n", index);
 469                         disable_usb_clocks(index);
 470                         return -EINVAL;
 471                 }
 472
 473                 ti_usb_phy_uboot_init(&usb_phy2_device);
 474                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 475                 dwc3_uboot_init(&usb_otg_ss2);
 476                 break;
 477         default:
 478                 printf("Invalid Controller Index\n");
 479         }
 480
 481         return 0;
 482 }
 483
 484 int board_usb_cleanup(int index, enum usb_init_type init)
 485 {
 486         switch (index) {
 487         case 0:
 488         case 1:
 489                 ti_usb_phy_uboot_exit(index);
 490                 dwc3_uboot_exit(index);
 491                 dwc3_omap_uboot_exit(index);
 492                 break;
 493         default:
 494                 printf("Invalid Controller Index\n");
 495         }
 496         disable_usb_clocks(index);
 497         return 0;
 498 }
 499
 500 int usb_gadget_handle_interrupts(int index)
 501 {
 502         u32 status;
 503
 504         status = dwc3_omap_uboot_interrupt_status(index);
 505         if (status)
 506                 dwc3_uboot_handle_interrupt(index);
 507
 508         return 0;
 509 }
 510 #endif
 511
 512 #ifdef CONFIG_DRIVER_TI_CPSW
 513
 514 /* Delay value to add to calibrated value */
 515 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 516 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 517 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 518 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 519 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 520 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 521 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 522 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 523 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 524 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 525
 526 static void cpsw_control(int enabled)
 527 {
 528         /* VTP can be added here */
 529 }
 530
 531 static struct cpsw_slave_data cpsw_slaves[] = {
 532         {
 533                 .slave_reg_ofs  = 0x208,
 534                 .sliver_reg_ofs = 0xd80,
 535                 .phy_addr       = 1,
 536         },
 537         {
 538                 .slave_reg_ofs  = 0x308,
 539                 .sliver_reg_ofs = 0xdc0,
 540                 .phy_addr       = 2,
 541         },
 542 };
 543
 544 static struct cpsw_platform_data cpsw_data = {
 545         .mdio_base              = CPSW_MDIO_BASE,
 546         .cpsw_base              = CPSW_BASE,
 547         .mdio_div               = 0xff,
 548         .channels               = 8,
 549         .cpdma_reg_ofs          = 0x800,
 550         .slaves                 = 1,
 551         .slave_data             = cpsw_slaves,
 552         .ale_reg_ofs            = 0xd00,
 553         .ale_entries            = 1024,
 554         .host_port_reg_ofs      = 0x108,
 555         .hw_stats_reg_ofs       = 0x900,
 556         .bd_ram_ofs             = 0x2000,
 557         .mac_control            = (1 << 5),
 558         .control                = cpsw_control,
 559         .host_port_num          = 0,
 560         .version                = CPSW_CTRL_VERSION_2,
 561 };
 562
 563 static u64 mac_to_u64(u8 mac[6])
 564 {
 565         int i;
 566         u64 addr = 0;
 567
 568         for (i = 0; i < 6; i++) {
 569                 addr <<= 8;
 570                 addr |= mac[i];
 571         }
 572
 573         return addr;
 574 }
 575
 576 static void u64_to_mac(u64 addr, u8 mac[6])
 577 {
 578         mac[5] = addr;
 579         mac[4] = addr >> 8;
 580         mac[3] = addr >> 16;
 581         mac[2] = addr >> 24;
 582         mac[1] = addr >> 32;
 583         mac[0] = addr >> 40;
 584 }
 585
 586 int board_eth_init(bd_t *bis)
 587 {
 588         int ret;
 589         uint8_t mac_addr[6];
 590         uint32_t mac_hi, mac_lo;
 591         uint32_t ctrl_val;
 592         int i;
 593         u64 mac1, mac2;
 594         u8 mac_addr1[6], mac_addr2[6];
 595         int num_macs;
 596
 597         /* try reading mac address from efuse */
 598         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 599         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 600         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 601         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 602         mac_addr[2] = mac_hi & 0xFF;
 603         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 604         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 605         mac_addr[5] = mac_lo & 0xFF;
 606
 607         if (!getenv("ethaddr")) {
 608                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 609
 610                 if (is_valid_ethaddr(mac_addr))
 611                         eth_setenv_enetaddr("ethaddr", mac_addr);
 612         }
 613
 614         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 615         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 616         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 617         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 618         mac_addr[2] = mac_hi & 0xFF;
 619         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 620         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 621         mac_addr[5] = mac_lo & 0xFF;
 622
 623         if (!getenv("eth1addr")) {
 624                 if (is_valid_ethaddr(mac_addr))
 625                         eth_setenv_enetaddr("eth1addr", mac_addr);
 626         }
 627
 628         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 629         ctrl_val |= 0x22;
 630         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 631
 632         /* The phy address for the AM572x IDK are different than x15 */
 633         if (board_is_am572x_idk()) {
 634                 cpsw_data.slave_data[0].phy_addr = 0;
 635                 cpsw_data.slave_data[1].phy_addr = 1;
 636         }
 637
 638         ret = cpsw_register(&cpsw_data);
 639         if (ret < 0)
 640                 printf("Error %d registering CPSW switch\n", ret);
 641
 642         /*
 643          * Export any Ethernet MAC addresses from EEPROM.
 644          * On AM57xx the 2 MAC addresses define the address range
 645          */
 646         board_ti_get_eth_mac_addr(0, mac_addr1);
 647         board_ti_get_eth_mac_addr(1, mac_addr2);
 648
 649         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 650                 mac1 = mac_to_u64(mac_addr1);
 651                 mac2 = mac_to_u64(mac_addr2);
 652
 653                 /* must contain an address range */
 654                 num_macs = mac2 - mac1 + 1;
 655                 /* <= 50 to protect against user programming error */
 656                 if (num_macs > 0 && num_macs <= 50) {
 657                         for (i = 0; i < num_macs; i++) {
 658                                 u64_to_mac(mac1 + i, mac_addr);
 659                                 if (is_valid_ethaddr(mac_addr)) {
 660                                         eth_setenv_enetaddr_by_index("eth",
 661                                                                      i + 2,
 662                                                                      mac_addr);
 663                                 }
 664                         }
 665                 }
 666         }
 667
 668         return ret;
 669 }
 670 #endif
 671
 672 #ifdef CONFIG_BOARD_EARLY_INIT_F
 673 /* VTT regulator enable */
 674 static inline void vtt_regulator_enable(void)
 675 {
 676         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 677                 return;
 678
 679         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 680         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 681 }
 682
 683 int board_early_init_f(void)
 684 {
 685         vtt_regulator_enable();
 686         return 0;
 687 }
 688 #endif