3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/gpio.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/sata.h>
21 #include <environment.h>
25 #ifdef CONFIG_DRIVER_TI_CPSW
29 DECLARE_GLOBAL_DATA_PTR;
32 #define GPIO_DDR_VTT_EN 203
34 const struct omap_sysinfo sysinfo = {
39 * Adjust I/O delays on the Tx control and data lines of each MAC port. This
40 * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
41 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
42 * essentially need to counteract the DRA7xx internal delay, and we do this
43 * by delaying the control and data lines. If not using this PHY, you probably
44 * don't need to do this stuff!
46 static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
54 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
56 while(io_dly[i].addr) {
57 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
59 delta = io_dly[i].dly;
60 reg_val = readl(io_dly[i].addr) & 0x3ff;
61 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
62 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
63 fine = (reg_val & 0x1F) + (delta & 0x1F);
64 fine = (fine > 0x1F) ? (0x1F) : (fine);
65 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
66 CFG_IO_DELAY_LOCK_MASK |
67 ((coarse << 5) | (fine));
68 writel(reg_val, io_dly[i].addr);
72 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
83 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
88 int board_late_init(void)
90 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
91 if (omap_revision() == DRA722_ES1_0)
92 setenv("board_name", "dra72x");
94 setenv("board_name", "dra7xx");
101 * @brief misc_init_r - Configure EVM board specific configurations
102 * such as power configurations, ethernet initialization as phase2 of
107 int misc_init_r(void)
112 static void do_set_mux32(u32 base,
113 struct pad_conf_entry const *array, int size)
116 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
118 for (i = 0; i < size; i++, pad++)
119 writel(pad->val, base + pad->offset);
122 void set_muxconf_regs_essential(void)
124 do_set_mux32((*ctrl)->control_padconf_core_base,
125 core_padconf_array_essential,
126 sizeof(core_padconf_array_essential) /
127 sizeof(struct pad_conf_entry));
130 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
131 int board_mmc_init(bd_t *bis)
133 omap_mmc_init(0, 0, 0, -1, -1);
134 omap_mmc_init(1, 0, 0, -1, -1);
139 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
140 int spl_start_uboot(void)
142 /* break into full u-boot on 'c' */
143 if (serial_tstc() && serial_getc() == 'c')
146 #ifdef CONFIG_SPL_ENV_SUPPORT
149 if (getenv_yesno("boot_os") != 1)
157 #ifdef CONFIG_DRIVER_TI_CPSW
159 /* Delay value to add to calibrated value */
160 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
161 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
162 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
163 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
164 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
165 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
166 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
167 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
168 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
169 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
171 extern u32 *const omap_si_rev;
173 static void cpsw_control(int enabled)
175 /* VTP can be added here */
180 static struct cpsw_slave_data cpsw_slaves[] = {
182 .slave_reg_ofs = 0x208,
183 .sliver_reg_ofs = 0xd80,
187 .slave_reg_ofs = 0x308,
188 .sliver_reg_ofs = 0xdc0,
193 static struct cpsw_platform_data cpsw_data = {
194 .mdio_base = CPSW_MDIO_BASE,
195 .cpsw_base = CPSW_BASE,
198 .cpdma_reg_ofs = 0x800,
200 .slave_data = cpsw_slaves,
201 .ale_reg_ofs = 0xd00,
203 .host_port_reg_ofs = 0x108,
204 .hw_stats_reg_ofs = 0x900,
205 .bd_ram_ofs = 0x2000,
206 .mac_control = (1 << 5),
207 .control = cpsw_control,
209 .version = CPSW_CTRL_VERSION_2,
212 int board_eth_init(bd_t *bis)
216 uint32_t mac_hi, mac_lo;
218 const struct io_delay io_dly[] = {
219 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
220 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
221 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
222 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
223 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
224 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
225 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
226 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
227 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
228 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
232 /* Adjust IO delay for RGMII tx path */
233 dra7xx_adj_io_delay(io_dly);
235 /* try reading mac address from efuse */
236 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
237 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
238 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
239 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
240 mac_addr[2] = mac_hi & 0xFF;
241 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
242 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
243 mac_addr[5] = mac_lo & 0xFF;
245 if (!getenv("ethaddr")) {
246 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
248 if (is_valid_ether_addr(mac_addr))
249 eth_setenv_enetaddr("ethaddr", mac_addr);
252 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
253 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
254 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
255 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
256 mac_addr[2] = mac_hi & 0xFF;
257 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
258 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
259 mac_addr[5] = mac_lo & 0xFF;
261 if (!getenv("eth1addr")) {
262 if (is_valid_ether_addr(mac_addr))
263 eth_setenv_enetaddr("eth1addr", mac_addr);
266 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
268 writel(ctrl_val, (*ctrl)->control_core_control_io1);
270 if (*omap_si_rev == DRA722_ES1_0)
271 cpsw_data.active_slave = 1;
273 ret = cpsw_register(&cpsw_data);
275 printf("Error %d registering CPSW switch\n", ret);
281 #ifdef CONFIG_BOARD_EARLY_INIT_F
282 /* VTT regulator enable */
283 static inline void vtt_regulator_enable(void)
285 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
288 /* Do not enable VTT for DRA722 */
289 if (omap_revision() == DRA722_ES1_0)
293 * EVM Rev G and later use gpio7_11 for DDR3 termination.
294 * This is safe enough to do on older revs.
296 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
297 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
300 int board_early_init_f(void)
302 vtt_regulator_enable();