git.sur5r.net Git - u-boot/blob - board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <linux/string.h>
  17 #include <asm/gpio.h>
  18 #include <usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <asm/omap_common.h>
  21 #include <asm/omap_sec_common.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/dra7xx_iodelay.h>
  24 #include <asm/emif.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/mmc_host_def.h>
  27 #include <asm/arch/sata.h>
  28 #include <environment.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32 #include <miiphy.h>
  33
  34 #include "mux_data.h"
  35 #include "../common/board_detect.h"
  36
  37 #define board_is_dra76x_evm()           board_ti_is("DRA76/7x")
  38 #define board_is_dra74x_evm()           board_ti_is("5777xCPU")
  39 #define board_is_dra72x_evm()           board_ti_is("DRA72x-T")
  40 #define board_is_dra71x_evm()           board_ti_is("DRA79x,D")
  41 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() &&       \
  42                                 (strncmp("H", board_ti_get_rev(), 1) <= 0))
  43 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() &&       \
  44                                 (strncmp("C", board_ti_get_rev(), 1) <= 0))
  45 #define board_ti_get_emif_size()        board_ti_get_emif1_size() +     \
  46                                         board_ti_get_emif2_size()
  47
  48 #ifdef CONFIG_DRIVER_TI_CPSW
  49 #include <cpsw.h>
  50 #endif
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 /* GPIO 7_11 */
  55 #define GPIO_DDR_VTT_EN 203
  56
  57 #define SYSINFO_BOARD_NAME_MAX_LEN      37
  58
  59 const struct omap_sysinfo sysinfo = {
  60         "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  61 };
  62
  63 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  64         .sdram_config_init              = 0x61851ab2,
  65         .sdram_config                   = 0x61851ab2,
  66         .sdram_config2                  = 0x08000000,
  67         .ref_ctrl                       = 0x000040F1,
  68         .ref_ctrl_final                 = 0x00001035,
  69         .sdram_tim1                     = 0xCCCF36B3,
  70         .sdram_tim2                     = 0x308F7FDA,
  71         .sdram_tim3                     = 0x427F88A8,
  72         .read_idle_ctrl                 = 0x00050000,
  73         .zq_config                      = 0x0007190B,
  74         .temp_alert_config              = 0x00000000,
  75         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  76         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  77         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  78         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  79         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  80         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  81         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  82         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  83         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  84         .emif_rd_wr_lvl_ctl             = 0x00000000,
  85         .emif_rd_wr_exec_thresh         = 0x00000305
  86 };
  87
  88 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  89         .sdram_config_init              = 0x61851B32,
  90         .sdram_config                   = 0x61851B32,
  91         .sdram_config2                  = 0x08000000,
  92         .ref_ctrl                       = 0x000040F1,
  93         .ref_ctrl_final                 = 0x00001035,
  94         .sdram_tim1                     = 0xCCCF36B3,
  95         .sdram_tim2                     = 0x308F7FDA,
  96         .sdram_tim3                     = 0x427F88A8,
  97         .read_idle_ctrl                 = 0x00050000,
  98         .zq_config                      = 0x0007190B,
  99         .temp_alert_config              = 0x00000000,
 100         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 101         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 102         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 103         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 104         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 105         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 106         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 107         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 108         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 109         .emif_rd_wr_lvl_ctl             = 0x00000000,
 110         .emif_rd_wr_exec_thresh         = 0x00000305
 111 };
 112
 113 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 114         .sdram_config_init              = 0x61862B32,
 115         .sdram_config                   = 0x61862B32,
 116         .sdram_config2                  = 0x08000000,
 117         .ref_ctrl                       = 0x0000514C,
 118         .ref_ctrl_final                 = 0x0000144A,
 119         .sdram_tim1                     = 0xD113781C,
 120         .sdram_tim2                     = 0x30717FE3,
 121         .sdram_tim3                     = 0x409F86A8,
 122         .read_idle_ctrl                 = 0x00050000,
 123         .zq_config                      = 0x5007190B,
 124         .temp_alert_config              = 0x00000000,
 125         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 126         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 127         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 128         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 129         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 130         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 131         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 132         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 133         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 134         .emif_rd_wr_lvl_ctl             = 0x00000000,
 135         .emif_rd_wr_exec_thresh         = 0x00000305
 136 };
 137
 138 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
 139         .sdram_config_init              = 0x61862BB2,
 140         .sdram_config                   = 0x61862BB2,
 141         .sdram_config2                  = 0x00000000,
 142         .ref_ctrl                       = 0x0000514D,
 143         .ref_ctrl_final                 = 0x0000144A,
 144         .sdram_tim1                     = 0xD1137824,
 145         .sdram_tim2                     = 0x30B37FE3,
 146         .sdram_tim3                     = 0x409F8AD8,
 147         .read_idle_ctrl                 = 0x00050000,
 148         .zq_config                      = 0x5007190B,
 149         .temp_alert_config              = 0x00000000,
 150         .emif_ddr_phy_ctlr_1_init       = 0x0824400E,
 151         .emif_ddr_phy_ctlr_1            = 0x0E24400E,
 152         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 153         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 154         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 155         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 156         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 157         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 158         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 159         .emif_rd_wr_lvl_ctl             = 0x00000000,
 160         .emif_rd_wr_exec_thresh         = 0x00000305
 161 };
 162
 163 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
 164         .sdram_config_init              = 0x61851ab2,
 165         .sdram_config                   = 0x61851ab2,
 166         .sdram_config2                  = 0x08000000,
 167         .ref_ctrl                       = 0x000040F1,
 168         .ref_ctrl_final                 = 0x00001035,
 169         .sdram_tim1                     = 0xCCCF36B3,
 170         .sdram_tim2                     = 0x30BF7FDA,
 171         .sdram_tim3                     = 0x427F8BA8,
 172         .read_idle_ctrl                 = 0x00050000,
 173         .zq_config                      = 0x0007190B,
 174         .temp_alert_config              = 0x00000000,
 175         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 176         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 177         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 178         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 179         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 180         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 181         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 182         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 183         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 184         .emif_rd_wr_lvl_ctl             = 0x00000000,
 185         .emif_rd_wr_exec_thresh         = 0x00000305
 186 };
 187
 188 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
 189         .sdram_config_init              = 0x61851B32,
 190         .sdram_config                   = 0x61851B32,
 191         .sdram_config2                  = 0x08000000,
 192         .ref_ctrl                       = 0x000040F1,
 193         .ref_ctrl_final                 = 0x00001035,
 194         .sdram_tim1                     = 0xCCCF36B3,
 195         .sdram_tim2                     = 0x308F7FDA,
 196         .sdram_tim3                     = 0x427F88A8,
 197         .read_idle_ctrl                 = 0x00050000,
 198         .zq_config                      = 0x0007190B,
 199         .temp_alert_config              = 0x00000000,
 200         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 201         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 202         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 203         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 204         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 205         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 206         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 207         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 208         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 209         .emif_rd_wr_lvl_ctl             = 0x00000000,
 210         .emif_rd_wr_exec_thresh         = 0x00000305
 211 };
 212
 213 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
 214         .sdram_config_init              = 0x61862B32,
 215         .sdram_config                   = 0x61862B32,
 216         .sdram_config2                  = 0x00000000,
 217         .ref_ctrl                       = 0x0000514C,
 218         .ref_ctrl_final                 = 0x0000144A,
 219         .sdram_tim1                     = 0xD113783C,
 220         .sdram_tim2                     = 0x30B47FE3,
 221         .sdram_tim3                     = 0x409F8AD8,
 222         .read_idle_ctrl                 = 0x00050000,
 223         .zq_config                      = 0x5007190B,
 224         .temp_alert_config              = 0x00000000,
 225         .emif_ddr_phy_ctlr_1_init       = 0x0824400D,
 226         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 227         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 228         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 229         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 230         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 231         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 232         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 233         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 234         .emif_rd_wr_lvl_ctl             = 0x00000000,
 235         .emif_rd_wr_exec_thresh         = 0x00000305
 236 };
 237
 238 const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
 239         .sdram_config_init              = 0x61862B32,
 240         .sdram_config                   = 0x61862B32,
 241         .sdram_config2                  = 0x00000000,
 242         .ref_ctrl                       = 0x0000514C,
 243         .ref_ctrl_final                 = 0x0000144A,
 244         .sdram_tim1                     = 0xD113781C,
 245         .sdram_tim2                     = 0x30B47FE3,
 246         .sdram_tim3                     = 0x409F8AD8,
 247         .read_idle_ctrl                 = 0x00050000,
 248         .zq_config                      = 0x5007190B,
 249         .temp_alert_config              = 0x00000000,
 250         .emif_ddr_phy_ctlr_1_init       = 0x0824400D,
 251         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 252         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 253         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 254         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 255         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 256         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 257         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 258         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 259         .emif_rd_wr_lvl_ctl             = 0x00000000,
 260         .emif_rd_wr_exec_thresh         = 0x00000305
 261 };
 262
 263 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 264 {
 265         u64 ram_size;
 266
 267         ram_size = board_ti_get_emif_size();
 268
 269         switch (omap_revision()) {
 270         case DRA752_ES1_0:
 271         case DRA752_ES1_1:
 272         case DRA752_ES2_0:
 273                 switch (emif_nr) {
 274                 case 1:
 275                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 276                                 *regs = &emif1_ddr3_532_mhz_1cs_2G;
 277                         else
 278                                 *regs = &emif1_ddr3_532_mhz_1cs;
 279                         break;
 280                 case 2:
 281                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 282                                 *regs = &emif2_ddr3_532_mhz_1cs_2G;
 283                         else
 284                                 *regs = &emif2_ddr3_532_mhz_1cs;
 285                         break;
 286                 }
 287                 break;
 288         case DRA762_ES1_0:
 289                 if (emif_nr == 1)
 290                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
 291                 else
 292                         *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
 293                 break;
 294         case DRA722_ES1_0:
 295         case DRA722_ES2_0:
 296         case DRA722_ES2_1:
 297                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 298                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 299                 else
 300                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
 301                 break;
 302         default:
 303                 *regs = &emif1_ddr3_532_mhz_1cs;
 304         }
 305 }
 306
 307 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
 308         .dmm_lisa_map_0 = 0x0,
 309         .dmm_lisa_map_1 = 0x80640300,
 310         .dmm_lisa_map_2 = 0xC0500220,
 311         .dmm_lisa_map_3 = 0xFF020100,
 312         .is_ma_present  = 0x1
 313 };
 314
 315 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 316         .dmm_lisa_map_0 = 0x0,
 317         .dmm_lisa_map_1 = 0x0,
 318         .dmm_lisa_map_2 = 0x80600100,
 319         .dmm_lisa_map_3 = 0xFF020100,
 320         .is_ma_present  = 0x1
 321 };
 322
 323 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
 324         .dmm_lisa_map_0 = 0x0,
 325         .dmm_lisa_map_1 = 0x0,
 326         .dmm_lisa_map_2 = 0x80740300,
 327         .dmm_lisa_map_3 = 0xFF020100,
 328         .is_ma_present  = 0x1
 329 };
 330
 331 /*
 332  * DRA722 EVM EMIF1 2GB CONFIGURATION
 333  * EMIF1 4 devices of 512Mb x 8 Micron
 334  */
 335 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
 336         .dmm_lisa_map_0 = 0x0,
 337         .dmm_lisa_map_1 = 0x0,
 338         .dmm_lisa_map_2 = 0x80700100,
 339         .dmm_lisa_map_3 = 0xFF020100,
 340         .is_ma_present  = 0x1
 341 };
 342
 343 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 344 {
 345         u64 ram_size;
 346
 347         ram_size = board_ti_get_emif_size();
 348
 349         switch (omap_revision()) {
 350         case DRA762_ES1_0:
 351         case DRA752_ES1_0:
 352         case DRA752_ES1_1:
 353         case DRA752_ES2_0:
 354                 if (ram_size > CONFIG_MAX_MEM_MAPPED)
 355                         *dmm_lisa_regs = &lisa_map_dra7_2GB;
 356                 else
 357                         *dmm_lisa_regs = &lisa_map_dra7_1536MB;
 358                 break;
 359         case DRA722_ES1_0:
 360         case DRA722_ES2_0:
 361         case DRA722_ES2_1:
 362         default:
 363                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 364                         *dmm_lisa_regs = &lisa_map_2G_x_2;
 365                 else
 366                         *dmm_lisa_regs = &lisa_map_2G_x_4;
 367                 break;
 368         }
 369 }
 370
 371 struct vcores_data dra752_volts = {
 372         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 373         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 374         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 375         .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
 376         .mpu.pmic       = &tps659038,
 377         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 378
 379         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 380         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 381         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 382         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 383         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 384         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 385         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 386         .eve.addr       = TPS659038_REG_ADDR_SMPS45,
 387         .eve.pmic       = &tps659038,
 388         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 389
 390         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 391         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 392         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 393         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 394         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 395         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 396         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 397         .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
 398         .gpu.pmic       = &tps659038,
 399         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 400
 401         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 402         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 403         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 404         .core.addr      = TPS659038_REG_ADDR_SMPS7,
 405         .core.pmic      = &tps659038,
 406
 407         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 408         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 409         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 410         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 411         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 412         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 413         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 414         .iva.addr       = TPS659038_REG_ADDR_SMPS8,
 415         .iva.pmic       = &tps659038,
 416         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 417 };
 418
 419 struct vcores_data dra76x_volts = {
 420         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 421         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 422         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 423         .mpu.addr       = LP87565_REG_ADDR_BUCK01,
 424         .mpu.pmic       = &lp87565,
 425         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 426
 427         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 428         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 429         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 430         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 431         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 432         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 433         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 434         .eve.addr       = TPS65917_REG_ADDR_SMPS1,
 435         .eve.pmic       = &tps659038,
 436         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 437
 438         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 439         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 440         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 441         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 442         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 443         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 444         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 445         .gpu.addr       = LP87565_REG_ADDR_BUCK23,
 446         .gpu.pmic       = &lp87565,
 447         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 448
 449         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 450         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 451         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 452         .core.addr      = TPS65917_REG_ADDR_SMPS3,
 453         .core.pmic      = &tps659038,
 454
 455         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 456         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 457         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 458         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 459         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 460         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 461         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 462         .iva.addr       = TPS65917_REG_ADDR_SMPS4,
 463         .iva.pmic       = &tps659038,
 464         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 465 };
 466
 467 struct vcores_data dra722_volts = {
 468         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 469         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 470         .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 471         .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
 472         .mpu.pmic       = &tps659038,
 473         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 474
 475         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 476         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 477         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 478         .core.addr      = TPS65917_REG_ADDR_SMPS2,
 479         .core.pmic      = &tps659038,
 480
 481         /*
 482          * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 483          * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 484          */
 485         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 486         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 487         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 488         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 489         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 490         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 491         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 492         .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
 493         .gpu.pmic       = &tps659038,
 494         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 495
 496         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 497         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 498         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 499         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 500         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 501         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 502         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 503         .eve.addr       = TPS65917_REG_ADDR_SMPS3,
 504         .eve.pmic       = &tps659038,
 505         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 506
 507         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 508         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 509         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 510         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 511         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 512         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 513         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 514         .iva.addr       = TPS65917_REG_ADDR_SMPS3,
 515         .iva.pmic       = &tps659038,
 516         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 517 };
 518
 519 struct vcores_data dra718_volts = {
 520         /*
 521          * In the case of dra71x GPU MPU and CORE
 522          * are all powered up by BUCK0 of LP873X PMIC
 523          */
 524         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 525         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 526         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 527         .mpu.addr       = LP873X_REG_ADDR_BUCK0,
 528         .mpu.pmic       = &lp8733,
 529         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 530
 531         .core.value[OPP_NOM]            = VDD_CORE_DRA7_NOM,
 532         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 533         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 534         .core.addr      = LP873X_REG_ADDR_BUCK0,
 535         .core.pmic      = &lp8733,
 536
 537         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 538         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 539         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 540         .gpu.addr       = LP873X_REG_ADDR_BUCK0,
 541         .gpu.pmic       = &lp8733,
 542         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 543
 544         /*
 545          * The DSPEVE and IVA rails are grouped on DRA71x-evm
 546          * and are powered by BUCK1 of LP873X PMIC
 547          */
 548         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 549         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 550         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 551         .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 552         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 553         .eve.addr       = LP873X_REG_ADDR_BUCK1,
 554         .eve.pmic       = &lp8733,
 555         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 556
 557         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 558         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 559         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 560         .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
 561         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 562         .iva.addr       = LP873X_REG_ADDR_BUCK1,
 563         .iva.pmic       = &lp8733,
 564         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 565 };
 566
 567 int get_voltrail_opp(int rail_offset)
 568 {
 569         int opp;
 570
 571         switch (rail_offset) {
 572         case VOLT_MPU:
 573                 opp = DRA7_MPU_OPP;
 574                 /* DRA71x supports only OPP_NOM for MPU */
 575                 if (board_is_dra71x_evm())
 576                         opp = OPP_NOM;
 577                 break;
 578         case VOLT_CORE:
 579                 opp = DRA7_CORE_OPP;
 580                 /* DRA71x supports only OPP_NOM for CORE */
 581                 if (board_is_dra71x_evm())
 582                         opp = OPP_NOM;
 583                 break;
 584         case VOLT_GPU:
 585                 opp = DRA7_GPU_OPP;
 586                 /* DRA71x supports only OPP_NOM for GPU */
 587                 if (board_is_dra71x_evm())
 588                         opp = OPP_NOM;
 589                 break;
 590         case VOLT_EVE:
 591                 opp = DRA7_DSPEVE_OPP;
 592                 /*
 593                  * DRA71x does not support OPP_OD for EVE.
 594                  * If OPP_OD is selected by menuconfig, fallback
 595                  * to OPP_NOM.
 596                  */
 597                 if (board_is_dra71x_evm() && opp == OPP_OD)
 598                         opp = OPP_NOM;
 599                 break;
 600         case VOLT_IVA:
 601                 opp = DRA7_IVA_OPP;
 602                 /*
 603                  * DRA71x does not support OPP_OD for IVA.
 604                  * If OPP_OD is selected by menuconfig, fallback
 605                  * to OPP_NOM.
 606                  */
 607                 if (board_is_dra71x_evm() && opp == OPP_OD)
 608                         opp = OPP_NOM;
 609                 break;
 610         default:
 611                 opp = OPP_NOM;
 612         }
 613
 614         return opp;
 615 }
 616
 617 /**
 618  * @brief board_init
 619  *
 620  * @return 0
 621  */
 622 int board_init(void)
 623 {
 624         gpmc_init();
 625         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 626
 627         return 0;
 628 }
 629
 630 int dram_init_banksize(void)
 631 {
 632         u64 ram_size;
 633
 634         ram_size = board_ti_get_emif_size();
 635
 636         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 637         gd->bd->bi_dram[0].size = get_effective_memsize();
 638         if (ram_size > CONFIG_MAX_MEM_MAPPED) {
 639                 gd->bd->bi_dram[1].start = 0x200000000;
 640                 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 641         }
 642
 643         return 0;
 644 }
 645
 646 int board_late_init(void)
 647 {
 648 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 649         char *name = "unknown";
 650
 651         if (is_dra72x()) {
 652                 if (board_is_dra72x_revc_or_later())
 653                         name = "dra72x-revc";
 654                 else if (board_is_dra71x_evm())
 655                         name = "dra71x";
 656                 else
 657                         name = "dra72x";
 658         } else if (is_dra76x()) {
 659                 name = "dra76x";
 660         } else {
 661                 name = "dra7xx";
 662         }
 663
 664         set_board_info_env(name);
 665
 666         /*
 667          * Default FIT boot on HS devices. Non FIT images are not allowed
 668          * on HS devices.
 669          */
 670         if (get_device_type() == HS_DEVICE)
 671                 env_set("boot_fit", "1");
 672
 673         omap_die_id_serial();
 674         omap_set_fastboot_vars();
 675
 676         /*
 677          * Hook the LDO1 regulator to EN pin. This applies only to LP8733
 678          * Rest all regulators are hooked to EN Pin at reset.
 679          */
 680         if (board_is_dra71x_evm())
 681                 palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
 682 #endif
 683         return 0;
 684 }
 685
 686 #ifdef CONFIG_SPL_BUILD
 687 void do_board_detect(void)
 688 {
 689         int rc;
 690
 691         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 692                                     CONFIG_EEPROM_CHIP_ADDRESS);
 693         if (rc)
 694                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 695 }
 696
 697 #else
 698
 699 void do_board_detect(void)
 700 {
 701         char *bname = NULL;
 702         int rc;
 703
 704         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 705                                     CONFIG_EEPROM_CHIP_ADDRESS);
 706         if (rc)
 707                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 708
 709         if (board_is_dra74x_evm()) {
 710                 bname = "DRA74x EVM";
 711         } else if (board_is_dra72x_evm()) {
 712                 bname = "DRA72x EVM";
 713         } else if (board_is_dra71x_evm()) {
 714                 bname = "DRA71x EVM";
 715         } else if (board_is_dra76x_evm()) {
 716                 bname = "DRA76x EVM";
 717         } else {
 718                 /* If EEPROM is not populated */
 719                 if (is_dra72x())
 720                         bname = "DRA72x EVM";
 721                 else
 722                         bname = "DRA74x EVM";
 723         }
 724
 725         if (bname)
 726                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 727                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 728 }
 729 #endif  /* CONFIG_SPL_BUILD */
 730
 731 void vcores_init(void)
 732 {
 733         if (board_is_dra74x_evm()) {
 734                 *omap_vcores = &dra752_volts;
 735         } else if (board_is_dra72x_evm()) {
 736                 *omap_vcores = &dra722_volts;
 737         } else if (board_is_dra71x_evm()) {
 738                 *omap_vcores = &dra718_volts;
 739         } else if (board_is_dra76x_evm()) {
 740                 *omap_vcores = &dra76x_volts;
 741         } else {
 742                 /* If EEPROM is not populated */
 743                 if (is_dra72x())
 744                         *omap_vcores = &dra722_volts;
 745                 else
 746                         *omap_vcores = &dra752_volts;
 747         }
 748 }
 749
 750 void set_muxconf_regs(void)
 751 {
 752         do_set_mux32((*ctrl)->control_padconf_core_base,
 753                      early_padconf, ARRAY_SIZE(early_padconf));
 754 }
 755
 756 #ifdef CONFIG_IODELAY_RECALIBRATION
 757 void recalibrate_iodelay(void)
 758 {
 759         struct pad_conf_entry const *pads, *delta_pads = NULL;
 760         struct iodelay_cfg_entry const *iodelay;
 761         int npads, niodelays, delta_npads = 0;
 762         int ret;
 763
 764         switch (omap_revision()) {
 765         case DRA722_ES1_0:
 766         case DRA722_ES2_0:
 767         case DRA722_ES2_1:
 768                 pads = dra72x_core_padconf_array_common;
 769                 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 770                 if (board_is_dra71x_evm()) {
 771                         pads = dra71x_core_padconf_array;
 772                         npads = ARRAY_SIZE(dra71x_core_padconf_array);
 773                         iodelay = dra71_iodelay_cfg_array;
 774                         niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
 775                 } else if (board_is_dra72x_revc_or_later()) {
 776                         delta_pads = dra72x_rgmii_padconf_array_revc;
 777                         delta_npads =
 778                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
 779                         iodelay = dra72_iodelay_cfg_array_revc;
 780                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
 781                 } else {
 782                         delta_pads = dra72x_rgmii_padconf_array_revb;
 783                         delta_npads =
 784                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
 785                         iodelay = dra72_iodelay_cfg_array_revb;
 786                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
 787                 }
 788                 break;
 789         case DRA752_ES1_0:
 790         case DRA752_ES1_1:
 791                 pads = dra74x_core_padconf_array;
 792                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 793                 iodelay = dra742_es1_1_iodelay_cfg_array;
 794                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 795                 break;
 796         case DRA762_ES1_0:
 797                 pads = dra76x_core_padconf_array;
 798                 npads = ARRAY_SIZE(dra76x_core_padconf_array);
 799                 iodelay = dra76x_es1_0_iodelay_cfg_array;
 800                 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
 801                 break;
 802         default:
 803         case DRA752_ES2_0:
 804                 pads = dra74x_core_padconf_array;
 805                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 806                 iodelay = dra742_es2_0_iodelay_cfg_array;
 807                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 808                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 809                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 810                                       RGMII1_ID_MODE_N_MASK);
 811                 break;
 812         }
 813         /* Setup I/O isolation */
 814         ret = __recalibrate_iodelay_start();
 815         if (ret)
 816                 goto err;
 817
 818         /* Do the muxing here */
 819         do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
 820
 821         /* Now do the weird minor deltas that should be safe */
 822         if (delta_npads)
 823                 do_set_mux32((*ctrl)->control_padconf_core_base,
 824                              delta_pads, delta_npads);
 825
 826         /* Setup IOdelay configuration */
 827         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
 828 err:
 829         /* Closeup.. remove isolation */
 830         __recalibrate_iodelay_end(ret);
 831 }
 832 #endif
 833
 834 #if defined(CONFIG_MMC)
 835 int board_mmc_init(bd_t *bis)
 836 {
 837         omap_mmc_init(0, 0, 0, -1, -1);
 838         omap_mmc_init(1, 0, 0, -1, -1);
 839         return 0;
 840 }
 841
 842 void board_mmc_poweron_ldo(uint voltage)
 843 {
 844         if (board_is_dra71x_evm()) {
 845                 if (voltage == LDO_VOLT_3V0)
 846                         voltage = 0x19;
 847                 else if (voltage == LDO_VOLT_1V8)
 848                         voltage = 0xa;
 849                 lp873x_mmc1_poweron_ldo(voltage);
 850         } else if (board_is_dra76x_evm()) {
 851                 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
 852         } else {
 853                 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
 854         }
 855 }
 856 #endif
 857
 858 #ifdef CONFIG_USB_DWC3
 859 static struct dwc3_device usb_otg_ss1 = {
 860         .maximum_speed = USB_SPEED_SUPER,
 861         .base = DRA7_USB_OTG_SS1_BASE,
 862         .tx_fifo_resize = false,
 863         .index = 0,
 864 };
 865
 866 static struct dwc3_omap_device usb_otg_ss1_glue = {
 867         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 868         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 869         .index = 0,
 870 };
 871
 872 static struct ti_usb_phy_device usb_phy1_device = {
 873         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 874         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 875         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 876         .index = 0,
 877 };
 878
 879 static struct dwc3_device usb_otg_ss2 = {
 880         .maximum_speed = USB_SPEED_SUPER,
 881         .base = DRA7_USB_OTG_SS2_BASE,
 882         .tx_fifo_resize = false,
 883         .index = 1,
 884 };
 885
 886 static struct dwc3_omap_device usb_otg_ss2_glue = {
 887         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 888         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 889         .index = 1,
 890 };
 891
 892 static struct ti_usb_phy_device usb_phy2_device = {
 893         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 894         .index = 1,
 895 };
 896
 897 int omap_xhci_board_usb_init(int index, enum usb_init_type init)
 898 {
 899         enable_usb_clocks(index);
 900         switch (index) {
 901         case 0:
 902                 if (init == USB_INIT_DEVICE) {
 903                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 904                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 905                 } else {
 906                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 907                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 908                 }
 909
 910                 ti_usb_phy_uboot_init(&usb_phy1_device);
 911                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 912                 dwc3_uboot_init(&usb_otg_ss1);
 913                 break;
 914         case 1:
 915                 if (init == USB_INIT_DEVICE) {
 916                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 917                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 918                 } else {
 919                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 920                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 921                 }
 922
 923                 ti_usb_phy_uboot_init(&usb_phy2_device);
 924                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 925                 dwc3_uboot_init(&usb_otg_ss2);
 926                 break;
 927         default:
 928                 printf("Invalid Controller Index\n");
 929         }
 930
 931         return 0;
 932 }
 933
 934 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
 935 {
 936         switch (index) {
 937         case 0:
 938         case 1:
 939                 ti_usb_phy_uboot_exit(index);
 940                 dwc3_uboot_exit(index);
 941                 dwc3_omap_uboot_exit(index);
 942                 break;
 943         default:
 944                 printf("Invalid Controller Index\n");
 945         }
 946         disable_usb_clocks(index);
 947         return 0;
 948 }
 949
 950 int usb_gadget_handle_interrupts(int index)
 951 {
 952         u32 status;
 953
 954         status = dwc3_omap_uboot_interrupt_status(index);
 955         if (status)
 956                 dwc3_uboot_handle_interrupt(index);
 957
 958         return 0;
 959 }
 960 #endif
 961
 962 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 963 int spl_start_uboot(void)
 964 {
 965         /* break into full u-boot on 'c' */
 966         if (serial_tstc() && serial_getc() == 'c')
 967                 return 1;
 968
 969 #ifdef CONFIG_SPL_ENV_SUPPORT
 970         env_init();
 971         env_load();
 972         if (env_get_yesno("boot_os") != 1)
 973                 return 1;
 974 #endif
 975
 976         return 0;
 977 }
 978 #endif
 979
 980 #ifdef CONFIG_DRIVER_TI_CPSW
 981 extern u32 *const omap_si_rev;
 982
 983 static void cpsw_control(int enabled)
 984 {
 985         /* VTP can be added here */
 986
 987         return;
 988 }
 989
 990 static struct cpsw_slave_data cpsw_slaves[] = {
 991         {
 992                 .slave_reg_ofs  = 0x208,
 993                 .sliver_reg_ofs = 0xd80,
 994                 .phy_addr       = 2,
 995         },
 996         {
 997                 .slave_reg_ofs  = 0x308,
 998                 .sliver_reg_ofs = 0xdc0,
 999                 .phy_addr       = 3,
1000         },
1001 };
1002
1003 static struct cpsw_platform_data cpsw_data = {
1004         .mdio_base              = CPSW_MDIO_BASE,
1005         .cpsw_base              = CPSW_BASE,
1006         .mdio_div               = 0xff,
1007         .channels               = 8,
1008         .cpdma_reg_ofs          = 0x800,
1009         .slaves                 = 2,
1010         .slave_data             = cpsw_slaves,
1011         .ale_reg_ofs            = 0xd00,
1012         .ale_entries            = 1024,
1013         .host_port_reg_ofs      = 0x108,
1014         .hw_stats_reg_ofs       = 0x900,
1015         .bd_ram_ofs             = 0x2000,
1016         .mac_control            = (1 << 5),
1017         .control                = cpsw_control,
1018         .host_port_num          = 0,
1019         .version                = CPSW_CTRL_VERSION_2,
1020 };
1021
1022 int board_eth_init(bd_t *bis)
1023 {
1024         int ret;
1025         uint8_t mac_addr[6];
1026         uint32_t mac_hi, mac_lo;
1027         uint32_t ctrl_val;
1028
1029         /* try reading mac address from efuse */
1030         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1031         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1032         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1033         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1034         mac_addr[2] = mac_hi & 0xFF;
1035         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1036         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1037         mac_addr[5] = mac_lo & 0xFF;
1038
1039         if (!env_get("ethaddr")) {
1040                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1041
1042                 if (is_valid_ethaddr(mac_addr))
1043                         eth_env_set_enetaddr("ethaddr", mac_addr);
1044         }
1045
1046         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1047         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1048         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1049         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1050         mac_addr[2] = mac_hi & 0xFF;
1051         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1052         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1053         mac_addr[5] = mac_lo & 0xFF;
1054
1055         if (!env_get("eth1addr")) {
1056                 if (is_valid_ethaddr(mac_addr))
1057                         eth_env_set_enetaddr("eth1addr", mac_addr);
1058         }
1059
1060         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1061         ctrl_val |= 0x22;
1062         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1063
1064         if (*omap_si_rev == DRA722_ES1_0)
1065                 cpsw_data.active_slave = 1;
1066
1067         if (board_is_dra72x_revc_or_later()) {
1068                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
1069                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
1070         }
1071
1072         ret = cpsw_register(&cpsw_data);
1073         if (ret < 0)
1074                 printf("Error %d registering CPSW switch\n", ret);
1075
1076         return ret;
1077 }
1078 #endif
1079
1080 #ifdef CONFIG_BOARD_EARLY_INIT_F
1081 /* VTT regulator enable */
1082 static inline void vtt_regulator_enable(void)
1083 {
1084         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1085                 return;
1086
1087         /* Do not enable VTT for DRA722 or DRA76x */
1088         if (is_dra72x() || is_dra76x())
1089                 return;
1090
1091         /*
1092          * EVM Rev G and later use gpio7_11 for DDR3 termination.
1093          * This is safe enough to do on older revs.
1094          */
1095         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1096         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1097 }
1098
1099 int board_early_init_f(void)
1100 {
1101         vtt_regulator_enable();
1102         return 0;
1103 }
1104 #endif
1105
1106 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1107 int ft_board_setup(void *blob, bd_t *bd)
1108 {
1109         ft_cpu_setup(blob, bd);
1110
1111         return 0;
1112 }
1113 #endif
1114
1115 #ifdef CONFIG_SPL_LOAD_FIT
1116 int board_fit_config_name_match(const char *name)
1117 {
1118         if (is_dra72x()) {
1119                 if (board_is_dra71x_evm()) {
1120                         if (!strcmp(name, "dra71-evm"))
1121                                 return 0;
1122                 }else if(board_is_dra72x_revc_or_later()) {
1123                         if (!strcmp(name, "dra72-evm-revc"))
1124                                 return 0;
1125                 } else if (!strcmp(name, "dra72-evm")) {
1126                         return 0;
1127                 }
1128         } else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
1129                 return 0;
1130         } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
1131                 return 0;
1132         }
1133
1134         return -1;
1135 }
1136 #endif
1137
1138 #ifdef CONFIG_TI_SECURE_DEVICE
1139 void board_fit_image_post_process(void **p_image, size_t *p_size)
1140 {
1141         secure_boot_verify_image(p_image, p_size);
1142 }
1143
1144 void board_tee_image_process(ulong tee_image, size_t tee_size)
1145 {
1146         secure_tee_install((u32)tee_image);
1147 }
1148
1149 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1150 #endif