git.sur5r.net Git - u-boot/blob - board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <linux/string.h>
  17 #include <asm/gpio.h>
  18 #include <usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <asm/omap_common.h>
  21 #include <asm/omap_sec_common.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/dra7xx_iodelay.h>
  24 #include <asm/emif.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/mmc_host_def.h>
  27 #include <asm/arch/sata.h>
  28 #include <environment.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32 #include <miiphy.h>
  33
  34 #include "mux_data.h"
  35 #include "../common/board_detect.h"
  36
  37 #define board_is_dra74x_evm()           board_ti_is("5777xCPU")
  38 #define board_is_dra72x_evm()           board_ti_is("DRA72x-T")
  39 #define board_is_dra71x_evm()           board_ti_is("DRA79x,D")
  40 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() &&       \
  41                                 (strncmp("H", board_ti_get_rev(), 1) <= 0))
  42 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() &&       \
  43                                 (strncmp("C", board_ti_get_rev(), 1) <= 0))
  44 #define board_ti_get_emif_size()        board_ti_get_emif1_size() +     \
  45                                         board_ti_get_emif2_size()
  46
  47 #ifdef CONFIG_DRIVER_TI_CPSW
  48 #include <cpsw.h>
  49 #endif
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 /* GPIO 7_11 */
  54 #define GPIO_DDR_VTT_EN 203
  55
  56 #define SYSINFO_BOARD_NAME_MAX_LEN      37
  57
  58 const struct omap_sysinfo sysinfo = {
  59         "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  60 };
  61
  62 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  63         .sdram_config_init              = 0x61851ab2,
  64         .sdram_config                   = 0x61851ab2,
  65         .sdram_config2                  = 0x08000000,
  66         .ref_ctrl                       = 0x000040F1,
  67         .ref_ctrl_final                 = 0x00001035,
  68         .sdram_tim1                     = 0xCCCF36B3,
  69         .sdram_tim2                     = 0x308F7FDA,
  70         .sdram_tim3                     = 0x427F88A8,
  71         .read_idle_ctrl                 = 0x00050000,
  72         .zq_config                      = 0x0007190B,
  73         .temp_alert_config              = 0x00000000,
  74         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  75         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  76         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  77         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  78         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  79         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  80         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  81         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  82         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  83         .emif_rd_wr_lvl_ctl             = 0x00000000,
  84         .emif_rd_wr_exec_thresh         = 0x00000305
  85 };
  86
  87 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  88         .sdram_config_init              = 0x61851B32,
  89         .sdram_config                   = 0x61851B32,
  90         .sdram_config2                  = 0x08000000,
  91         .ref_ctrl                       = 0x000040F1,
  92         .ref_ctrl_final                 = 0x00001035,
  93         .sdram_tim1                     = 0xCCCF36B3,
  94         .sdram_tim2                     = 0x308F7FDA,
  95         .sdram_tim3                     = 0x427F88A8,
  96         .read_idle_ctrl                 = 0x00050000,
  97         .zq_config                      = 0x0007190B,
  98         .temp_alert_config              = 0x00000000,
  99         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 100         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 101         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 102         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 103         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 104         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 105         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 106         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 107         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 108         .emif_rd_wr_lvl_ctl             = 0x00000000,
 109         .emif_rd_wr_exec_thresh         = 0x00000305
 110 };
 111
 112 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 113         .sdram_config_init              = 0x61862B32,
 114         .sdram_config                   = 0x61862B32,
 115         .sdram_config2                  = 0x08000000,
 116         .ref_ctrl                       = 0x0000514C,
 117         .ref_ctrl_final                 = 0x0000144A,
 118         .sdram_tim1                     = 0xD113781C,
 119         .sdram_tim2                     = 0x30717FE3,
 120         .sdram_tim3                     = 0x409F86A8,
 121         .read_idle_ctrl                 = 0x00050000,
 122         .zq_config                      = 0x5007190B,
 123         .temp_alert_config              = 0x00000000,
 124         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 125         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 126         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 127         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 128         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 129         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 130         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 131         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 132         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 133         .emif_rd_wr_lvl_ctl             = 0x00000000,
 134         .emif_rd_wr_exec_thresh         = 0x00000305
 135 };
 136
 137 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
 138         .sdram_config_init              = 0x61862BB2,
 139         .sdram_config                   = 0x61862BB2,
 140         .sdram_config2                  = 0x00000000,
 141         .ref_ctrl                       = 0x0000514D,
 142         .ref_ctrl_final                 = 0x0000144A,
 143         .sdram_tim1                     = 0xD1137824,
 144         .sdram_tim2                     = 0x30B37FE3,
 145         .sdram_tim3                     = 0x409F8AD8,
 146         .read_idle_ctrl                 = 0x00050000,
 147         .zq_config                      = 0x5007190B,
 148         .temp_alert_config              = 0x00000000,
 149         .emif_ddr_phy_ctlr_1_init       = 0x0824400E,
 150         .emif_ddr_phy_ctlr_1            = 0x0E24400E,
 151         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 152         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 153         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 154         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 155         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 156         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 157         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 158         .emif_rd_wr_lvl_ctl             = 0x00000000,
 159         .emif_rd_wr_exec_thresh         = 0x00000305
 160 };
 161
 162 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
 163         .sdram_config_init              = 0x61851ab2,
 164         .sdram_config                   = 0x61851ab2,
 165         .sdram_config2                  = 0x08000000,
 166         .ref_ctrl                       = 0x000040F1,
 167         .ref_ctrl_final                 = 0x00001035,
 168         .sdram_tim1                     = 0xCCCF36B3,
 169         .sdram_tim2                     = 0x30BF7FDA,
 170         .sdram_tim3                     = 0x427F8BA8,
 171         .read_idle_ctrl                 = 0x00050000,
 172         .zq_config                      = 0x0007190B,
 173         .temp_alert_config              = 0x00000000,
 174         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 175         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 176         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 177         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 178         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 179         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 180         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 181         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 182         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 183         .emif_rd_wr_lvl_ctl             = 0x00000000,
 184         .emif_rd_wr_exec_thresh         = 0x00000305
 185 };
 186
 187 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
 188         .sdram_config_init              = 0x61851B32,
 189         .sdram_config                   = 0x61851B32,
 190         .sdram_config2                  = 0x08000000,
 191         .ref_ctrl                       = 0x000040F1,
 192         .ref_ctrl_final                 = 0x00001035,
 193         .sdram_tim1                     = 0xCCCF36B3,
 194         .sdram_tim2                     = 0x308F7FDA,
 195         .sdram_tim3                     = 0x427F88A8,
 196         .read_idle_ctrl                 = 0x00050000,
 197         .zq_config                      = 0x0007190B,
 198         .temp_alert_config              = 0x00000000,
 199         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 200         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 201         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 202         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 203         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 204         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 205         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 206         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 207         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 208         .emif_rd_wr_lvl_ctl             = 0x00000000,
 209         .emif_rd_wr_exec_thresh         = 0x00000305
 210 };
 211
 212 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 213 {
 214         u64 ram_size;
 215
 216         ram_size = board_ti_get_emif_size();
 217
 218         switch (omap_revision()) {
 219         case DRA752_ES1_0:
 220         case DRA752_ES1_1:
 221         case DRA752_ES2_0:
 222                 switch (emif_nr) {
 223                 case 1:
 224                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 225                                 *regs = &emif1_ddr3_532_mhz_1cs_2G;
 226                         else
 227                                 *regs = &emif1_ddr3_532_mhz_1cs;
 228                         break;
 229                 case 2:
 230                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 231                                 *regs = &emif2_ddr3_532_mhz_1cs_2G;
 232                         else
 233                                 *regs = &emif2_ddr3_532_mhz_1cs;
 234                         break;
 235                 }
 236                 break;
 237         case DRA722_ES1_0:
 238         case DRA722_ES2_0:
 239                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 240                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 241                 else
 242                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
 243                 break;
 244         default:
 245                 *regs = &emif1_ddr3_532_mhz_1cs;
 246         }
 247 }
 248
 249 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
 250         .dmm_lisa_map_0 = 0x0,
 251         .dmm_lisa_map_1 = 0x80640300,
 252         .dmm_lisa_map_2 = 0xC0500220,
 253         .dmm_lisa_map_3 = 0xFF020100,
 254         .is_ma_present  = 0x1
 255 };
 256
 257 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 258         .dmm_lisa_map_0 = 0x0,
 259         .dmm_lisa_map_1 = 0x0,
 260         .dmm_lisa_map_2 = 0x80600100,
 261         .dmm_lisa_map_3 = 0xFF020100,
 262         .is_ma_present  = 0x1
 263 };
 264
 265 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
 266         .dmm_lisa_map_0 = 0x0,
 267         .dmm_lisa_map_1 = 0x0,
 268         .dmm_lisa_map_2 = 0x80740300,
 269         .dmm_lisa_map_3 = 0xFF020100,
 270         .is_ma_present  = 0x1
 271 };
 272
 273 /*
 274  * DRA722 EVM EMIF1 2GB CONFIGURATION
 275  * EMIF1 4 devices of 512Mb x 8 Micron
 276  */
 277 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
 278         .dmm_lisa_map_0 = 0x0,
 279         .dmm_lisa_map_1 = 0x0,
 280         .dmm_lisa_map_2 = 0x80700100,
 281         .dmm_lisa_map_3 = 0xFF020100,
 282         .is_ma_present  = 0x1
 283 };
 284
 285 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 286 {
 287         u64 ram_size;
 288
 289         ram_size = board_ti_get_emif_size();
 290
 291         switch (omap_revision()) {
 292         case DRA752_ES1_0:
 293         case DRA752_ES1_1:
 294         case DRA752_ES2_0:
 295                 if (ram_size > CONFIG_MAX_MEM_MAPPED)
 296                         *dmm_lisa_regs = &lisa_map_dra7_2GB;
 297                 else
 298                         *dmm_lisa_regs = &lisa_map_dra7_1536MB;
 299                 break;
 300         case DRA722_ES1_0:
 301         case DRA722_ES2_0:
 302         default:
 303                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 304                         *dmm_lisa_regs = &lisa_map_2G_x_2;
 305                 else
 306                         *dmm_lisa_regs = &lisa_map_2G_x_4;
 307                 break;
 308         }
 309 }
 310
 311 struct vcores_data dra752_volts = {
 312         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 313         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 314         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 315         .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
 316         .mpu.pmic       = &tps659038,
 317         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 318
 319         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 320         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 321         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 322         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 323         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 324         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 325         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 326         .eve.addr       = TPS659038_REG_ADDR_SMPS45,
 327         .eve.pmic       = &tps659038,
 328         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 329
 330         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 331         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 332         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 333         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 334         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 335         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 336         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 337         .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
 338         .gpu.pmic       = &tps659038,
 339         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 340
 341         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 342         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 343         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 344         .core.addr      = TPS659038_REG_ADDR_SMPS7,
 345         .core.pmic      = &tps659038,
 346
 347         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 348         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 349         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 350         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 351         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 352         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 353         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 354         .iva.addr       = TPS659038_REG_ADDR_SMPS8,
 355         .iva.pmic       = &tps659038,
 356         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 357 };
 358
 359 struct vcores_data dra722_volts = {
 360         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 361         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 362         .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 363         .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
 364         .mpu.pmic       = &tps659038,
 365         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 366
 367         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 368         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 369         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 370         .core.addr      = TPS65917_REG_ADDR_SMPS2,
 371         .core.pmic      = &tps659038,
 372
 373         /*
 374          * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 375          * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 376          */
 377         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 378         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 379         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 380         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 381         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 382         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 383         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 384         .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
 385         .gpu.pmic       = &tps659038,
 386         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 387
 388         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 389         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 390         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 391         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 392         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 393         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 394         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 395         .eve.addr       = TPS65917_REG_ADDR_SMPS3,
 396         .eve.pmic       = &tps659038,
 397         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 398
 399         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 400         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 401         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 402         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 403         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 404         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 405         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 406         .iva.addr       = TPS65917_REG_ADDR_SMPS3,
 407         .iva.pmic       = &tps659038,
 408         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 409 };
 410
 411 struct vcores_data dra718_volts = {
 412         /*
 413          * In the case of dra71x GPU MPU and CORE
 414          * are all powered up by BUCK0 of LP873X PMIC
 415          */
 416         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 417         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 418         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 419         .mpu.addr       = LP873X_REG_ADDR_BUCK0,
 420         .mpu.pmic       = &lp8733,
 421         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 422
 423         .core.value[OPP_NOM]            = VDD_CORE_DRA7_NOM,
 424         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 425         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 426         .core.addr      = LP873X_REG_ADDR_BUCK0,
 427         .core.pmic      = &lp8733,
 428
 429         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 430         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 431         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 432         .gpu.addr       = LP873X_REG_ADDR_BUCK0,
 433         .gpu.pmic       = &lp8733,
 434         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 435
 436         /*
 437          * The DSPEVE and IVA rails are grouped on DRA71x-evm
 438          * and are powered by BUCK1 of LP873X PMIC
 439          */
 440         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 441         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 442         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 443         .eve.addr       = LP873X_REG_ADDR_BUCK1,
 444         .eve.pmic       = &lp8733,
 445         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 446
 447         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 448         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 449         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 450         .iva.addr       = LP873X_REG_ADDR_BUCK1,
 451         .iva.pmic       = &lp8733,
 452         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 453 };
 454
 455 int get_voltrail_opp(int rail_offset)
 456 {
 457         int opp;
 458
 459         /*
 460          * DRA71x supports only OPP_NOM.
 461          */
 462         if (board_is_dra71x_evm())
 463                 return OPP_NOM;
 464
 465         switch (rail_offset) {
 466         case VOLT_MPU:
 467                 opp = DRA7_MPU_OPP;
 468                 break;
 469         case VOLT_CORE:
 470                 opp = DRA7_CORE_OPP;
 471                 break;
 472         case VOLT_GPU:
 473                 opp = DRA7_GPU_OPP;
 474                 break;
 475         case VOLT_EVE:
 476                 opp = DRA7_DSPEVE_OPP;
 477                 break;
 478         case VOLT_IVA:
 479                 opp = DRA7_IVA_OPP;
 480                 break;
 481         default:
 482                 opp = OPP_NOM;
 483         }
 484
 485         return opp;
 486 }
 487
 488 /**
 489  * @brief board_init
 490  *
 491  * @return 0
 492  */
 493 int board_init(void)
 494 {
 495         gpmc_init();
 496         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 497
 498         return 0;
 499 }
 500
 501 int dram_init_banksize(void)
 502 {
 503         u64 ram_size;
 504
 505         ram_size = board_ti_get_emif_size();
 506
 507         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 508         gd->bd->bi_dram[0].size = get_effective_memsize();
 509         if (ram_size > CONFIG_MAX_MEM_MAPPED) {
 510                 gd->bd->bi_dram[1].start = 0x200000000;
 511                 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 512         }
 513
 514         return 0;
 515 }
 516
 517 int board_late_init(void)
 518 {
 519 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 520         char *name = "unknown";
 521
 522         if (is_dra72x()) {
 523                 if (board_is_dra72x_revc_or_later())
 524                         name = "dra72x-revc";
 525                 else if (board_is_dra71x_evm())
 526                         name = "dra71x";
 527                 else
 528                         name = "dra72x";
 529         } else {
 530                 name = "dra7xx";
 531         }
 532
 533         set_board_info_env(name);
 534
 535         /*
 536          * Default FIT boot on HS devices. Non FIT images are not allowed
 537          * on HS devices.
 538          */
 539         if (get_device_type() == HS_DEVICE)
 540                 setenv("boot_fit", "1");
 541
 542         omap_die_id_serial();
 543 #endif
 544         return 0;
 545 }
 546
 547 #ifdef CONFIG_SPL_BUILD
 548 void do_board_detect(void)
 549 {
 550         int rc;
 551
 552         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 553                                     CONFIG_EEPROM_CHIP_ADDRESS);
 554         if (rc)
 555                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 556 }
 557
 558 #else
 559
 560 void do_board_detect(void)
 561 {
 562         char *bname = NULL;
 563         int rc;
 564
 565         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 566                                     CONFIG_EEPROM_CHIP_ADDRESS);
 567         if (rc)
 568                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 569
 570         if (board_is_dra74x_evm()) {
 571                 bname = "DRA74x EVM";
 572         } else if (board_is_dra72x_evm()) {
 573                 bname = "DRA72x EVM";
 574         } else if (board_is_dra71x_evm()) {
 575                 bname = "DRA71x EVM";
 576         } else {
 577                 /* If EEPROM is not populated */
 578                 if (is_dra72x())
 579                         bname = "DRA72x EVM";
 580                 else
 581                         bname = "DRA74x EVM";
 582         }
 583
 584         if (bname)
 585                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 586                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 587 }
 588 #endif  /* CONFIG_SPL_BUILD */
 589
 590 void vcores_init(void)
 591 {
 592         if (board_is_dra74x_evm()) {
 593                 *omap_vcores = &dra752_volts;
 594         } else if (board_is_dra72x_evm()) {
 595                 *omap_vcores = &dra722_volts;
 596         } else if (board_is_dra71x_evm()) {
 597                 *omap_vcores = &dra718_volts;
 598         } else {
 599                 /* If EEPROM is not populated */
 600                 if (is_dra72x())
 601                         *omap_vcores = &dra722_volts;
 602                 else
 603                         *omap_vcores = &dra752_volts;
 604         }
 605 }
 606
 607 void set_muxconf_regs(void)
 608 {
 609         do_set_mux32((*ctrl)->control_padconf_core_base,
 610                      early_padconf, ARRAY_SIZE(early_padconf));
 611 }
 612
 613 #ifdef CONFIG_IODELAY_RECALIBRATION
 614 void recalibrate_iodelay(void)
 615 {
 616         struct pad_conf_entry const *pads, *delta_pads = NULL;
 617         struct iodelay_cfg_entry const *iodelay;
 618         int npads, niodelays, delta_npads = 0;
 619         int ret;
 620
 621         switch (omap_revision()) {
 622         case DRA722_ES1_0:
 623         case DRA722_ES2_0:
 624                 pads = dra72x_core_padconf_array_common;
 625                 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 626                 if (board_is_dra71x_evm()) {
 627                         pads = dra71x_core_padconf_array;
 628                         npads = ARRAY_SIZE(dra71x_core_padconf_array);
 629                         iodelay = dra71_iodelay_cfg_array;
 630                         niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
 631                 } else if (board_is_dra72x_revc_or_later()) {
 632                         delta_pads = dra72x_rgmii_padconf_array_revc;
 633                         delta_npads =
 634                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
 635                         iodelay = dra72_iodelay_cfg_array_revc;
 636                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
 637                 } else {
 638                         delta_pads = dra72x_rgmii_padconf_array_revb;
 639                         delta_npads =
 640                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
 641                         iodelay = dra72_iodelay_cfg_array_revb;
 642                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
 643                 }
 644                 break;
 645         case DRA752_ES1_0:
 646         case DRA752_ES1_1:
 647                 pads = dra74x_core_padconf_array;
 648                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 649                 iodelay = dra742_es1_1_iodelay_cfg_array;
 650                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 651                 break;
 652         default:
 653         case DRA752_ES2_0:
 654                 pads = dra74x_core_padconf_array;
 655                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 656                 iodelay = dra742_es2_0_iodelay_cfg_array;
 657                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 658                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 659                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 660                                       RGMII1_ID_MODE_N_MASK);
 661                 break;
 662         }
 663         /* Setup I/O isolation */
 664         ret = __recalibrate_iodelay_start();
 665         if (ret)
 666                 goto err;
 667
 668         /* Do the muxing here */
 669         do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
 670
 671         /* Now do the weird minor deltas that should be safe */
 672         if (delta_npads)
 673                 do_set_mux32((*ctrl)->control_padconf_core_base,
 674                              delta_pads, delta_npads);
 675
 676         /* Setup IOdelay configuration */
 677         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
 678 err:
 679         /* Closeup.. remove isolation */
 680         __recalibrate_iodelay_end(ret);
 681 }
 682 #endif
 683
 684 #if defined(CONFIG_GENERIC_MMC)
 685 int board_mmc_init(bd_t *bis)
 686 {
 687         omap_mmc_init(0, 0, 0, -1, -1);
 688         omap_mmc_init(1, 0, 0, -1, -1);
 689         return 0;
 690 }
 691 #endif
 692
 693 #ifdef CONFIG_USB_DWC3
 694 static struct dwc3_device usb_otg_ss1 = {
 695         .maximum_speed = USB_SPEED_SUPER,
 696         .base = DRA7_USB_OTG_SS1_BASE,
 697         .tx_fifo_resize = false,
 698         .index = 0,
 699 };
 700
 701 static struct dwc3_omap_device usb_otg_ss1_glue = {
 702         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 703         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 704         .index = 0,
 705 };
 706
 707 static struct ti_usb_phy_device usb_phy1_device = {
 708         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 709         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 710         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 711         .index = 0,
 712 };
 713
 714 static struct dwc3_device usb_otg_ss2 = {
 715         .maximum_speed = USB_SPEED_SUPER,
 716         .base = DRA7_USB_OTG_SS2_BASE,
 717         .tx_fifo_resize = false,
 718         .index = 1,
 719 };
 720
 721 static struct dwc3_omap_device usb_otg_ss2_glue = {
 722         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 723         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 724         .index = 1,
 725 };
 726
 727 static struct ti_usb_phy_device usb_phy2_device = {
 728         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 729         .index = 1,
 730 };
 731
 732 int board_usb_init(int index, enum usb_init_type init)
 733 {
 734         enable_usb_clocks(index);
 735         switch (index) {
 736         case 0:
 737                 if (init == USB_INIT_DEVICE) {
 738                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 739                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 740                 } else {
 741                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 742                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 743                 }
 744
 745                 ti_usb_phy_uboot_init(&usb_phy1_device);
 746                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 747                 dwc3_uboot_init(&usb_otg_ss1);
 748                 break;
 749         case 1:
 750                 if (init == USB_INIT_DEVICE) {
 751                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 752                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 753                 } else {
 754                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 755                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 756                 }
 757
 758                 ti_usb_phy_uboot_init(&usb_phy2_device);
 759                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 760                 dwc3_uboot_init(&usb_otg_ss2);
 761                 break;
 762         default:
 763                 printf("Invalid Controller Index\n");
 764         }
 765
 766         return 0;
 767 }
 768
 769 int board_usb_cleanup(int index, enum usb_init_type init)
 770 {
 771         switch (index) {
 772         case 0:
 773         case 1:
 774                 ti_usb_phy_uboot_exit(index);
 775                 dwc3_uboot_exit(index);
 776                 dwc3_omap_uboot_exit(index);
 777                 break;
 778         default:
 779                 printf("Invalid Controller Index\n");
 780         }
 781         disable_usb_clocks(index);
 782         return 0;
 783 }
 784
 785 int usb_gadget_handle_interrupts(int index)
 786 {
 787         u32 status;
 788
 789         status = dwc3_omap_uboot_interrupt_status(index);
 790         if (status)
 791                 dwc3_uboot_handle_interrupt(index);
 792
 793         return 0;
 794 }
 795 #endif
 796
 797 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 798 int spl_start_uboot(void)
 799 {
 800         /* break into full u-boot on 'c' */
 801         if (serial_tstc() && serial_getc() == 'c')
 802                 return 1;
 803
 804 #ifdef CONFIG_SPL_ENV_SUPPORT
 805         env_init();
 806         env_relocate_spec();
 807         if (getenv_yesno("boot_os") != 1)
 808                 return 1;
 809 #endif
 810
 811         return 0;
 812 }
 813 #endif
 814
 815 #ifdef CONFIG_DRIVER_TI_CPSW
 816 extern u32 *const omap_si_rev;
 817
 818 static void cpsw_control(int enabled)
 819 {
 820         /* VTP can be added here */
 821
 822         return;
 823 }
 824
 825 static struct cpsw_slave_data cpsw_slaves[] = {
 826         {
 827                 .slave_reg_ofs  = 0x208,
 828                 .sliver_reg_ofs = 0xd80,
 829                 .phy_addr       = 2,
 830         },
 831         {
 832                 .slave_reg_ofs  = 0x308,
 833                 .sliver_reg_ofs = 0xdc0,
 834                 .phy_addr       = 3,
 835         },
 836 };
 837
 838 static struct cpsw_platform_data cpsw_data = {
 839         .mdio_base              = CPSW_MDIO_BASE,
 840         .cpsw_base              = CPSW_BASE,
 841         .mdio_div               = 0xff,
 842         .channels               = 8,
 843         .cpdma_reg_ofs          = 0x800,
 844         .slaves                 = 2,
 845         .slave_data             = cpsw_slaves,
 846         .ale_reg_ofs            = 0xd00,
 847         .ale_entries            = 1024,
 848         .host_port_reg_ofs      = 0x108,
 849         .hw_stats_reg_ofs       = 0x900,
 850         .bd_ram_ofs             = 0x2000,
 851         .mac_control            = (1 << 5),
 852         .control                = cpsw_control,
 853         .host_port_num          = 0,
 854         .version                = CPSW_CTRL_VERSION_2,
 855 };
 856
 857 int board_eth_init(bd_t *bis)
 858 {
 859         int ret;
 860         uint8_t mac_addr[6];
 861         uint32_t mac_hi, mac_lo;
 862         uint32_t ctrl_val;
 863
 864         /* try reading mac address from efuse */
 865         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 866         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 867         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 868         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 869         mac_addr[2] = mac_hi & 0xFF;
 870         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 871         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 872         mac_addr[5] = mac_lo & 0xFF;
 873
 874         if (!getenv("ethaddr")) {
 875                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 876
 877                 if (is_valid_ethaddr(mac_addr))
 878                         eth_setenv_enetaddr("ethaddr", mac_addr);
 879         }
 880
 881         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 882         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 883         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 884         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 885         mac_addr[2] = mac_hi & 0xFF;
 886         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 887         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 888         mac_addr[5] = mac_lo & 0xFF;
 889
 890         if (!getenv("eth1addr")) {
 891                 if (is_valid_ethaddr(mac_addr))
 892                         eth_setenv_enetaddr("eth1addr", mac_addr);
 893         }
 894
 895         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 896         ctrl_val |= 0x22;
 897         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 898
 899         if (*omap_si_rev == DRA722_ES1_0)
 900                 cpsw_data.active_slave = 1;
 901
 902         if (board_is_dra72x_revc_or_later()) {
 903                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
 904                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
 905         }
 906
 907         ret = cpsw_register(&cpsw_data);
 908         if (ret < 0)
 909                 printf("Error %d registering CPSW switch\n", ret);
 910
 911         return ret;
 912 }
 913 #endif
 914
 915 #ifdef CONFIG_BOARD_EARLY_INIT_F
 916 /* VTT regulator enable */
 917 static inline void vtt_regulator_enable(void)
 918 {
 919         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 920                 return;
 921
 922         /* Do not enable VTT for DRA722 */
 923         if (is_dra72x())
 924                 return;
 925
 926         /*
 927          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 928          * This is safe enough to do on older revs.
 929          */
 930         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 931         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 932 }
 933
 934 int board_early_init_f(void)
 935 {
 936         vtt_regulator_enable();
 937         return 0;
 938 }
 939 #endif
 940
 941 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 942 int ft_board_setup(void *blob, bd_t *bd)
 943 {
 944         ft_cpu_setup(blob, bd);
 945
 946         return 0;
 947 }
 948 #endif
 949
 950 #ifdef CONFIG_SPL_LOAD_FIT
 951 int board_fit_config_name_match(const char *name)
 952 {
 953         if (is_dra72x()) {
 954                 if (board_is_dra71x_evm()) {
 955                         if (!strcmp(name, "dra71-evm"))
 956                                 return 0;
 957                 }else if(board_is_dra72x_revc_or_later()) {
 958                         if (!strcmp(name, "dra72-evm-revc"))
 959                                 return 0;
 960                 } else if (!strcmp(name, "dra72-evm")) {
 961                         return 0;
 962                 }
 963         } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
 964                 return 0;
 965         }
 966
 967         return -1;
 968 }
 969 #endif
 970
 971 #ifdef CONFIG_TI_SECURE_DEVICE
 972 void board_fit_image_post_process(void **p_image, size_t *p_size)
 973 {
 974         secure_boot_verify_image(p_image, p_size);
 975 }
 976
 977 void board_tee_image_process(ulong tee_image, size_t tee_size)
 978 {
 979         secure_tee_install((u32)tee_image);
 980 }
 981
 982 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 983 #endif