3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/mmc_host_def.h>
20 #ifdef CONFIG_USB_EHCI
22 #include <asm/arch/ehci.h>
23 #include <asm/ehci-omap.h>
26 #ifdef CONFIG_DRIVER_TI_CPSW
30 DECLARE_GLOBAL_DATA_PTR;
32 const struct omap_sysinfo sysinfo = {
37 * Adjust I/O delays on the Tx control and data lines of each MAC port. This
38 * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
39 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
40 * essentially need to counteract the DRA7xx internal delay, and we do this
41 * by delaying the control and data lines. If not using this PHY, you probably
42 * don't need to do this stuff!
44 static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
52 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
54 while(io_dly[i].addr) {
55 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
57 delta = io_dly[i].dly;
58 reg_val = readl(io_dly[i].addr) & 0x3ff;
59 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
60 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
61 fine = (reg_val & 0x1F) + (delta & 0x1F);
62 fine = (fine > 0x1F) ? (0x1F) : (fine);
63 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
64 CFG_IO_DELAY_LOCK_MASK |
65 ((coarse << 5) | (fine));
66 writel(reg_val, io_dly[i].addr);
70 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
81 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
87 * @brief misc_init_r - Configure EVM board specific configurations
88 * such as power configurations, ethernet initialization as phase2 of
98 static void do_set_mux32(u32 base,
99 struct pad_conf_entry const *array, int size)
102 struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
104 for (i = 0; i < size; i++, pad++)
105 writel(pad->val, base + pad->offset);
108 void set_muxconf_regs_essential(void)
110 do_set_mux32((*ctrl)->control_padconf_core_base,
111 core_padconf_array_essential,
112 sizeof(core_padconf_array_essential) /
113 sizeof(struct pad_conf_entry));
116 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
117 int board_mmc_init(bd_t *bis)
119 omap_mmc_init(0, 0, 0, -1, -1);
120 omap_mmc_init(1, 0, 0, -1, -1);
125 #ifdef CONFIG_DRIVER_TI_CPSW
127 /* Delay value to add to calibrated value */
128 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
129 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
130 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
131 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
132 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
133 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
134 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
135 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
136 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
137 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
139 static void cpsw_control(int enabled)
141 /* VTP can be added here */
146 static struct cpsw_slave_data cpsw_slaves[] = {
148 .slave_reg_ofs = 0x208,
149 .sliver_reg_ofs = 0xd80,
153 .slave_reg_ofs = 0x308,
154 .sliver_reg_ofs = 0xdc0,
159 static struct cpsw_platform_data cpsw_data = {
160 .mdio_base = CPSW_MDIO_BASE,
161 .cpsw_base = CPSW_BASE,
164 .cpdma_reg_ofs = 0x800,
166 .slave_data = cpsw_slaves,
167 .ale_reg_ofs = 0xd00,
169 .host_port_reg_ofs = 0x108,
170 .hw_stats_reg_ofs = 0x900,
171 .bd_ram_ofs = 0x2000,
172 .mac_control = (1 << 5),
173 .control = cpsw_control,
175 .version = CPSW_CTRL_VERSION_2,
178 int board_eth_init(bd_t *bis)
182 uint32_t mac_hi, mac_lo;
184 const struct io_delay io_dly[] = {
185 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
186 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
187 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
188 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
189 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
190 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
191 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
192 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
193 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
194 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
198 /* Adjust IO delay for RGMII tx path */
199 dra7xx_adj_io_delay(io_dly);
201 /* try reading mac address from efuse */
202 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
203 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
204 mac_addr[0] = mac_hi & 0xFF;
205 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
206 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
207 mac_addr[3] = mac_lo & 0xFF;
208 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
209 mac_addr[5] = (mac_lo & 0xFF0000) >> 16;
211 if (!getenv("ethaddr")) {
212 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
214 if (is_valid_ether_addr(mac_addr))
215 eth_setenv_enetaddr("ethaddr", mac_addr);
217 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
219 writel(ctrl_val, (*ctrl)->control_core_control_io1);
221 ret = cpsw_register(&cpsw_data);
223 printf("Error %d registering CPSW switch\n", ret);