3 * Texas Instruments Incorporated, <www.ti.com>
5 * Sricharan R <r.sricharan@ti.com>
6 * Nishant Kamat <nskamat@ti.com>
8 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _MUX_DATA_DRA7XX_H_
11 #define _MUX_DATA_DRA7XX_H_
13 #include <asm/arch/mux_dra7xx.h>
15 const struct pad_conf_entry core_padconf_array_essential[] = {
16 {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
17 {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
18 {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
19 {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
20 {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
21 {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
22 {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
23 {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
24 #if defined(CONFIG_NOR)
25 /* NOR only pin-mux */
26 {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
27 {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
28 {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
29 {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
30 {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
31 {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
32 {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
33 {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
34 {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
35 {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
36 {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
37 {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
38 {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
39 {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
40 {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
41 {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
42 {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
43 {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
44 {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
45 {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
46 {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
47 {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
48 {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
49 {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
50 {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
51 {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
52 {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
55 {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
56 {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
57 {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
58 {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
59 {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
60 {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
61 {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
62 {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
63 {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
64 {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
66 #if (CONFIG_CONS_INDEX == 1)
67 {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
68 {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
69 {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
70 {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
71 #elif (CONFIG_CONS_INDEX == 3)
72 {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
73 {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
75 {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
76 {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
77 {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
78 {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
80 {RGMII0_TXCTL, (M0) },
85 {RGMII0_RXC, (IEN | M0) },
86 {RGMII0_RXCTL, (IEN | M0) },
87 {RGMII0_RXD3, (IEN | M0) },
88 {RGMII0_RXD2, (IEN | M0) },
89 {RGMII0_RXD1, (IEN | M0) },
90 {RGMII0_RXD0, (IEN | M0) },
97 {VIN2A_D18, (IEN | M3)},
98 {VIN2A_D19, (IEN | M3)},
99 {VIN2A_D20, (IEN | M3)},
100 {VIN2A_D21, (IEN | M3)},
101 {VIN2A_D22, (IEN | M3)},
102 {VIN2A_D23, (IEN | M3)},
103 #if defined(CONFIG_NAND) || defined(CONFIG_NOR)
104 /* NAND / NOR pin-mux */
105 {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
106 {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
107 {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
108 {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
109 {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
110 {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
111 {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
112 {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
113 {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
114 {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
115 {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
116 {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
117 {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
118 {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
119 {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
120 {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
121 {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
122 {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
123 {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
124 {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
125 {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
126 {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
127 /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
130 {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
131 {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
132 {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
133 {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
134 {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
135 {GPMC_A18, (M1)}, /* QSPI1_SCLK */
136 {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
137 {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
138 {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
139 {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
140 #endif /* CONFIG_NAND || CONFIG_NOR */
141 {USB2_DRVVBUS, (M0 | IEN | FSC) },
142 {SPI1_CS1, (PEN | IDIS | M14) },
144 #endif /* _MUX_DATA_DRA7XX_H_ */