3 * Texas Instruments Incorporated, <www.ti.com>
5 * Sricharan R <r.sricharan@ti.com>
6 * Nishant Kamat <nskamat@ti.com>
8 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _MUX_DATA_DRA7XX_H_
11 #define _MUX_DATA_DRA7XX_H_
13 #include <asm/arch/mux_dra7xx.h>
15 const struct pad_conf_entry core_padconf_array_essential[] = {
16 {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
17 {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
18 {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
19 {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
20 {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
21 {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
22 {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
23 {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
24 {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
25 {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
26 {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
27 {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
28 {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
29 {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
30 {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
31 {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
32 {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
33 {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
34 #if (CONFIG_CONS_INDEX == 1)
35 {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
36 {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
37 {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
38 {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
39 #elif (CONFIG_CONS_INDEX == 3)
40 {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
41 {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
43 {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
44 {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
45 {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
46 {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
48 {RGMII0_TXCTL, (M0) },
53 {RGMII0_RXC, (IEN | M0) },
54 {RGMII0_RXCTL, (IEN | M0) },
55 {RGMII0_RXD3, (IEN | M0) },
56 {RGMII0_RXD2, (IEN | M0) },
57 {RGMII0_RXD1, (IEN | M0) },
58 {RGMII0_RXD0, (IEN | M0) },
65 {VIN2A_D18, (IEN | M3)},
66 {VIN2A_D19, (IEN | M3)},
67 {VIN2A_D20, (IEN | M3)},
68 {VIN2A_D21, (IEN | M3)},
69 {VIN2A_D22, (IEN | M3)},
70 {VIN2A_D23, (IEN | M3)},
72 /* NAND / NOR pin-mux */
73 {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
74 {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
75 {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
76 {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
77 {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
78 {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
79 {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
80 {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
81 {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
82 {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
83 {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
84 {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
85 {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
86 {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
87 {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
88 {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
89 {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
90 {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
91 {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
92 {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
93 {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
94 {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
95 /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
98 {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
99 {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
100 {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
101 {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
102 {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
103 {GPMC_A18, (M1)}, /* QSPI1_SCLK */
104 {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
105 {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
106 {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
107 {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
108 #endif /* CONFIG_NAND */
109 {USB2_DRVVBUS, (M0 | IEN | FSC) },
111 #endif /* _MUX_DATA_DRA7XX_H_ */