2 * (C) Copyright 2004-2011
3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/mem.h>
18 #include <asm/arch/mux.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/mmc_host_def.h>
23 #include <asm/mach-types.h>
24 #include <linux/mtd/nand.h>
27 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
28 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
30 DECLARE_GLOBAL_DATA_PTR;
32 static u32 omap3_evm_version;
34 u32 get_omap3_evm_rev(void)
36 return omap3_evm_version;
39 static void omap3_evm_get_revision(void)
41 #if defined(CONFIG_CMD_NET)
43 * Board revision can be ascertained only by identifying
44 * the Ethernet chipset.
48 /* Ethernet PHY ID is stored at ID_REV register */
49 smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
50 printf("Read back SMSC id 0x%x\n", smsc_id);
53 /* SMSC9115 chipset */
55 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
57 /* SMSC 9220 chipset */
60 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
63 #if defined(CONFIG_STATIC_BOARD_REV)
65 * Look for static defintion of the board revision
67 omap3_evm_version = CONFIG_STATIC_BOARD_REV;
70 * Fallback to the default above.
72 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
74 #endif /* CONFIG_CMD_NET */
77 #ifdef CONFIG_USB_OMAP3
79 * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
81 u8 omap3_evm_need_extvbus(void)
85 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
94 * Description: Early hardware init.
98 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
99 /* board id for Linux */
100 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
101 /* boot param addr */
102 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
107 #ifdef CONFIG_SPL_BUILD
109 * Routine: get_board_mem_timings
110 * Description: If we use SPL then there is no x-loader nor config header
111 * so we have to setup the DDR timings ourself on the first bank. This
112 * provides the timing values back to the function that configures
115 void get_board_mem_timings(struct board_sdrc_timings *timings)
120 * We need to identify what PoP memory is on the board so that
121 * we know what timings to use. To map the ID values please see
124 identify_nand_chip(&pop_mfr, &pop_id);
126 if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
128 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
129 timings->ctrla = HYNIX_V_ACTIMA_200;
130 timings->ctrlb = HYNIX_V_ACTIMB_200;
133 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
134 timings->ctrla = MICRON_V_ACTIMA_165;
135 timings->ctrlb = MICRON_V_ACTIMB_165;
137 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
138 timings->mr = MICRON_V_MR_165;
143 * Routine: misc_init_r
144 * Description: Init ethernet (done here so udelay works)
146 int misc_init_r(void)
149 #ifdef CONFIG_SYS_I2C_OMAP34XX
150 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
153 #if defined(CONFIG_CMD_NET)
156 omap3_evm_get_revision();
158 #if defined(CONFIG_CMD_NET)
167 * Routine: set_muxconf_regs
168 * Description: Setting up the configuration Mux registers specific to the
169 * hardware. Many pins need to be moved from protect to primary
172 void set_muxconf_regs(void)
177 #ifdef CONFIG_CMD_NET
179 * Routine: setup_net_chip
180 * Description: Setting up the configuration GPMC registers specific to the
183 static void setup_net_chip(void)
185 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
187 /* Configure GPMC registers */
188 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
189 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
190 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
191 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
192 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
193 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
194 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
196 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
197 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
198 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
199 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
200 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
201 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
202 &ctrl_base->gpmc_nadv_ale);
206 * Reset the ethernet chip.
208 static void reset_net_chip(void)
213 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
214 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
216 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
219 ret = gpio_request(rst_gpio, "");
221 printf("Unable to get GPIO %d\n", rst_gpio);
225 /* Configure as output */
226 gpio_direction_output(rst_gpio, 0);
228 /* Send a pulse on the GPIO pin */
229 gpio_set_value(rst_gpio, 1);
231 gpio_set_value(rst_gpio, 0);
233 gpio_set_value(rst_gpio, 1);
236 int board_eth_init(bd_t *bis)
239 #ifdef CONFIG_SMC911X
240 #define STR_ENV_ETHADDR "ethaddr"
242 struct eth_device *dev;
245 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
247 if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
248 dev = eth_get_dev_by_index(0);
250 eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
252 printf("omap3evm: Couldn't get eth device\n");
259 #endif /* CONFIG_CMD_NET */
261 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
262 int board_mmc_init(bd_t *bis)
264 return omap_mmc_init(0, 0, 0, -1, -1);