2 * Keystone : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
15 #include <asm/arch/ddr3.h>
16 #include <asm/arch/psc_defs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/ti-common/ti-aemif.h>
19 #include <asm/ti-common/keystone_net.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #if defined(CONFIG_TI_AEMIF)
24 static struct aemif_config aemif_configs[] = {
26 .mode = AEMIF_MODE_NAND,
34 .width = AEMIF_WIDTH_8,
43 ddr3_size = ddr3_init();
45 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
46 CONFIG_MAX_RAM_BANK_SIZE);
47 #if defined(CONFIG_TI_AEMIF)
48 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
52 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
54 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30);
61 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
66 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
68 int get_eth_env_param(char *env_name)
73 env = getenv(env_name);
75 res = simple_strtol(env, NULL, 0);
80 int board_eth_init(bd_t *bis)
85 char link_type_name[32];
88 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
90 /* By default, select PA PLL clock as PA clock source */
91 #ifndef CONFIG_SOC_K2G
92 if (psc_enable_module(KS2_LPSC_PA))
95 if (psc_enable_module(KS2_LPSC_CPGMAC))
97 if (psc_enable_module(KS2_LPSC_CRYPTO))
100 if (cpu_is_k2e() || cpu_is_k2l())
103 port_num = get_num_eth_ports();
105 for (j = 0; j < port_num; j++) {
106 sprintf(link_type_name, "sgmii%d_link_type", j);
107 res = get_eth_env_param(link_type_name);
109 eth_priv_cfg[j].sgmii_link_type = res;
111 keystone2_emac_initialize(ð_priv_cfg[j]);
119 #ifdef CONFIG_SPL_BUILD
120 void spl_board_init(void)
122 spl_init_keystone_plls();
123 preloader_console_init();
126 u32 spl_boot_device(void)
128 #if defined(CONFIG_SPL_SPI_LOAD)
129 return BOOT_DEVICE_SPI;
131 puts("Unknown boot device\n");
137 #ifdef CONFIG_OF_BOARD_SETUP
138 int ft_board_setup(void *blob, bd_t *bd)
148 int unitrd_fixup = 0;
150 env = getenv("mem_lpae");
151 lpae = env && simple_strtol(env, NULL, 0);
152 env = getenv("uinitrd_fixup");
153 unitrd_fixup = env && simple_strtol(env, NULL, 0);
157 ddr3a_size = ddr3_get_size();
158 if ((ddr3a_size != 8) && (ddr3a_size != 4))
163 start[0] = bd->bi_dram[0].start;
164 size[0] = bd->bi_dram[0].size;
166 /* adjust memory start address for LPAE */
168 start[0] -= CONFIG_SYS_SDRAM_BASE;
169 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
172 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
173 size[1] = ((u64)ddr3a_size - 2) << 30;
174 start[1] = 0x880000000;
178 /* reserve memory at start of bank */
179 env = getenv("mem_reserve_head");
181 start[0] += ustrtoul(env, &endp, 0);
182 size[0] -= ustrtoul(env, &endp, 0);
185 env = getenv("mem_reserve");
187 size[0] -= ustrtoul(env, &endp, 0);
189 fdt_fixup_memory_banks(blob, start, size, nbanks);
191 /* Fix up the initrd */
192 if (lpae && unitrd_fixup) {
195 u64 initrd_start, initrd_end;
197 nodeoffset = fdt_path_offset(blob, "/chosen");
198 if (nodeoffset >= 0) {
199 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
200 "linux,initrd-start", NULL);
201 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
202 "linux,initrd-end", NULL);
203 if (prop1 && prop2) {
204 initrd_start = __be32_to_cpu(*prop1);
205 initrd_start -= CONFIG_SYS_SDRAM_BASE;
206 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
207 initrd_start = __cpu_to_be64(initrd_start);
208 initrd_end = __be32_to_cpu(*prop2);
209 initrd_end -= CONFIG_SYS_SDRAM_BASE;
210 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
211 initrd_end = __cpu_to_be64(initrd_end);
213 err = fdt_delprop(blob, nodeoffset,
214 "linux,initrd-start");
216 puts("error deleting initrd-start\n");
218 err = fdt_delprop(blob, nodeoffset,
221 puts("error deleting initrd-end\n");
223 err = fdt_setprop(blob, nodeoffset,
224 "linux,initrd-start",
226 sizeof(initrd_start));
228 puts("error adding initrd-start\n");
230 err = fdt_setprop(blob, nodeoffset,
235 puts("error adding linux,initrd-end\n");
243 void ft_board_setup_ex(void *blob, bd_t *bd)
250 env = getenv("mem_lpae");
251 lpae = env && simple_strtol(env, NULL, 0);
255 * the initrd and other reserved memory areas are
256 * embedded in in the DTB itslef. fix up these addresses
259 reserve_start = (u64 *)((char *)blob +
260 fdt_off_mem_rsvmap(blob));
262 *reserve_start = __cpu_to_be64(*reserve_start);
263 size = __cpu_to_be64(*(reserve_start + 1));
265 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
267 CONFIG_SYS_LPAE_SDRAM_BASE;
269 __cpu_to_be64(*reserve_start);
277 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
279 #endif /* CONFIG_OF_BOARD_SETUP */