2 * Keystone : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
15 #include <asm/arch/ddr3.h>
16 #include <asm/arch/psc_defs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/ti-common/ti-aemif.h>
19 #include <asm/ti-common/keystone_net.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #if defined(CONFIG_TI_AEMIF)
24 static struct aemif_config aemif_configs[] = {
26 .mode = AEMIF_MODE_NAND,
34 .width = AEMIF_WIDTH_8,
43 ddr3_size = ddr3_init();
45 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
46 CONFIG_MAX_RAM_BANK_SIZE);
47 #if defined(CONFIG_TI_AEMIF)
48 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
52 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
58 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
63 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
65 int get_eth_env_param(char *env_name)
70 env = getenv(env_name);
72 res = simple_strtol(env, NULL, 0);
77 int board_eth_init(bd_t *bis)
82 char link_type_name[32];
85 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
87 /* By default, select PA PLL clock as PA clock source */
88 #ifndef CONFIG_SOC_K2G
89 if (psc_enable_module(KS2_LPSC_PA))
92 if (psc_enable_module(KS2_LPSC_CPGMAC))
94 if (psc_enable_module(KS2_LPSC_CRYPTO))
97 if (cpu_is_k2e() || cpu_is_k2l())
100 port_num = get_num_eth_ports();
102 for (j = 0; j < port_num; j++) {
103 sprintf(link_type_name, "sgmii%d_link_type", j);
104 res = get_eth_env_param(link_type_name);
106 eth_priv_cfg[j].sgmii_link_type = res;
108 keystone2_emac_initialize(ð_priv_cfg[j]);
116 #ifdef CONFIG_SPL_BUILD
117 void spl_board_init(void)
119 spl_init_keystone_plls();
120 preloader_console_init();
123 u32 spl_boot_device(void)
125 #if defined(CONFIG_SPL_SPI_LOAD)
126 return BOOT_DEVICE_SPI;
128 puts("Unknown boot device\n");
134 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
135 int ft_board_setup(void *blob, bd_t *bd)
145 int unitrd_fixup = 0;
147 env = getenv("mem_lpae");
148 lpae = env && simple_strtol(env, NULL, 0);
149 env = getenv("uinitrd_fixup");
150 unitrd_fixup = env && simple_strtol(env, NULL, 0);
154 ddr3a_size = ddr3_get_size();
155 if ((ddr3a_size != 8) && (ddr3a_size != 4))
160 start[0] = bd->bi_dram[0].start;
161 size[0] = bd->bi_dram[0].size;
163 /* adjust memory start address for LPAE */
165 start[0] -= CONFIG_SYS_SDRAM_BASE;
166 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
169 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
170 size[1] = ((u64)ddr3a_size - 2) << 30;
171 start[1] = 0x880000000;
175 /* reserve memory at start of bank */
176 env = getenv("mem_reserve_head");
178 start[0] += ustrtoul(env, &endp, 0);
179 size[0] -= ustrtoul(env, &endp, 0);
182 env = getenv("mem_reserve");
184 size[0] -= ustrtoul(env, &endp, 0);
186 fdt_fixup_memory_banks(blob, start, size, nbanks);
188 /* Fix up the initrd */
189 if (lpae && unitrd_fixup) {
192 u64 initrd_start, initrd_end;
194 nodeoffset = fdt_path_offset(blob, "/chosen");
195 if (nodeoffset >= 0) {
196 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
197 "linux,initrd-start", NULL);
198 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
199 "linux,initrd-end", NULL);
200 if (prop1 && prop2) {
201 initrd_start = __be32_to_cpu(*prop1);
202 initrd_start -= CONFIG_SYS_SDRAM_BASE;
203 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
204 initrd_start = __cpu_to_be64(initrd_start);
205 initrd_end = __be32_to_cpu(*prop2);
206 initrd_end -= CONFIG_SYS_SDRAM_BASE;
207 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
208 initrd_end = __cpu_to_be64(initrd_end);
210 err = fdt_delprop(blob, nodeoffset,
211 "linux,initrd-start");
213 puts("error deleting initrd-start\n");
215 err = fdt_delprop(blob, nodeoffset,
218 puts("error deleting initrd-end\n");
220 err = fdt_setprop(blob, nodeoffset,
221 "linux,initrd-start",
223 sizeof(initrd_start));
225 puts("error adding initrd-start\n");
227 err = fdt_setprop(blob, nodeoffset,
232 puts("error adding linux,initrd-end\n");
240 void ft_board_setup_ex(void *blob, bd_t *bd)
247 env = getenv("mem_lpae");
248 lpae = env && simple_strtol(env, NULL, 0);
252 * the initrd and other reserved memory areas are
253 * embedded in in the DTB itslef. fix up these addresses
256 reserve_start = (u64 *)((char *)blob +
257 fdt_off_mem_rsvmap(blob));
259 *reserve_start = __cpu_to_be64(*reserve_start);
260 size = __cpu_to_be64(*(reserve_start + 1));
262 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
264 CONFIG_SYS_LPAE_SDRAM_BASE;
266 __cpu_to_be64(*reserve_start);
274 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);