2 * Keystone : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
15 #include <asm/arch/ddr3.h>
16 #include <asm/arch/psc_defs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/ti-common/ti-aemif.h>
19 #include <asm/ti-common/keystone_net.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 static struct aemif_config aemif_configs[] = {
25 .mode = AEMIF_MODE_NAND,
33 .width = AEMIF_WIDTH_8,
41 ddr3_size = ddr3_init();
43 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
44 CONFIG_MAX_RAM_BANK_SIZE);
45 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
47 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
53 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
58 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
60 int get_eth_env_param(char *env_name)
65 env = getenv(env_name);
67 res = simple_strtol(env, NULL, 0);
72 int board_eth_init(bd_t *bis)
77 char link_type_name[32];
80 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
82 /* By default, select PA PLL clock as PA clock source */
83 #ifndef CONFIG_SOC_K2G
84 if (psc_enable_module(KS2_LPSC_PA))
87 if (psc_enable_module(KS2_LPSC_CPGMAC))
89 if (psc_enable_module(KS2_LPSC_CRYPTO))
92 if (cpu_is_k2e() || cpu_is_k2l())
95 port_num = get_num_eth_ports();
97 for (j = 0; j < port_num; j++) {
98 sprintf(link_type_name, "sgmii%d_link_type", j);
99 res = get_eth_env_param(link_type_name);
101 eth_priv_cfg[j].sgmii_link_type = res;
103 keystone2_emac_initialize(ð_priv_cfg[j]);
111 #ifdef CONFIG_SPL_BUILD
112 void spl_board_init(void)
114 spl_init_keystone_plls();
115 preloader_console_init();
118 u32 spl_boot_device(void)
120 #if defined(CONFIG_SPL_SPI_LOAD)
121 return BOOT_DEVICE_SPI;
123 puts("Unknown boot device\n");
129 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
130 int ft_board_setup(void *blob, bd_t *bd)
140 int unitrd_fixup = 0;
142 env = getenv("mem_lpae");
143 lpae = env && simple_strtol(env, NULL, 0);
144 env = getenv("uinitrd_fixup");
145 unitrd_fixup = env && simple_strtol(env, NULL, 0);
149 env = getenv("ddr3a_size");
151 ddr3a_size = simple_strtol(env, NULL, 10);
152 if ((ddr3a_size != 8) && (ddr3a_size != 4))
157 start[0] = bd->bi_dram[0].start;
158 size[0] = bd->bi_dram[0].size;
160 /* adjust memory start address for LPAE */
162 start[0] -= CONFIG_SYS_SDRAM_BASE;
163 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
166 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
167 size[1] = ((u64)ddr3a_size - 2) << 30;
168 start[1] = 0x880000000;
172 /* reserve memory at start of bank */
173 env = getenv("mem_reserve_head");
175 start[0] += ustrtoul(env, &endp, 0);
176 size[0] -= ustrtoul(env, &endp, 0);
179 env = getenv("mem_reserve");
181 size[0] -= ustrtoul(env, &endp, 0);
183 fdt_fixup_memory_banks(blob, start, size, nbanks);
185 /* Fix up the initrd */
186 if (lpae && unitrd_fixup) {
189 u64 initrd_start, initrd_end;
191 nodeoffset = fdt_path_offset(blob, "/chosen");
192 if (nodeoffset >= 0) {
193 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
194 "linux,initrd-start", NULL);
195 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
196 "linux,initrd-end", NULL);
197 if (prop1 && prop2) {
198 initrd_start = __be32_to_cpu(*prop1);
199 initrd_start -= CONFIG_SYS_SDRAM_BASE;
200 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
201 initrd_start = __cpu_to_be64(initrd_start);
202 initrd_end = __be32_to_cpu(*prop2);
203 initrd_end -= CONFIG_SYS_SDRAM_BASE;
204 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
205 initrd_end = __cpu_to_be64(initrd_end);
207 err = fdt_delprop(blob, nodeoffset,
208 "linux,initrd-start");
210 puts("error deleting initrd-start\n");
212 err = fdt_delprop(blob, nodeoffset,
215 puts("error deleting initrd-end\n");
217 err = fdt_setprop(blob, nodeoffset,
218 "linux,initrd-start",
220 sizeof(initrd_start));
222 puts("error adding initrd-start\n");
224 err = fdt_setprop(blob, nodeoffset,
229 puts("error adding linux,initrd-end\n");
237 void ft_board_setup_ex(void *blob, bd_t *bd)
244 env = getenv("mem_lpae");
245 lpae = env && simple_strtol(env, NULL, 0);
249 * the initrd and other reserved memory areas are
250 * embedded in in the DTB itslef. fix up these addresses
253 reserve_start = (u64 *)((char *)blob +
254 fdt_off_mem_rsvmap(blob));
256 *reserve_start = __cpu_to_be64(*reserve_start);
257 size = __cpu_to_be64(*(reserve_start + 1));
259 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
261 CONFIG_SYS_LPAE_SDRAM_BASE;
263 __cpu_to_be64(*reserve_start);
271 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);