2 * Keystone : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
15 #include <asm/arch/ddr3.h>
16 #include <asm/arch/psc_defs.h>
17 #include <asm/ti-common/ti-aemif.h>
18 #include <asm/ti-common/keystone_net.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static struct aemif_config aemif_configs[] = {
24 .mode = AEMIF_MODE_NAND,
32 .width = AEMIF_WIDTH_8,
40 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
41 CONFIG_MAX_RAM_BANK_SIZE);
42 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
43 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE);
49 gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
54 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
55 int get_eth_env_param(char *env_name)
60 env = getenv(env_name);
62 res = simple_strtol(env, NULL, 0);
67 int board_eth_init(bd_t *bis)
72 char link_type_name[32];
74 /* By default, select PA PLL clock as PA clock source */
75 if (psc_enable_module(KS2_LPSC_PA))
77 if (psc_enable_module(KS2_LPSC_CPGMAC))
79 if (psc_enable_module(KS2_LPSC_CRYPTO))
81 pass_pll_pa_clk_enable();
83 port_num = get_num_eth_ports();
85 for (j = 0; j < port_num; j++) {
86 sprintf(link_type_name, "sgmii%d_link_type", j);
87 res = get_eth_env_param(link_type_name);
89 eth_priv_cfg[j].sgmii_link_type = res;
91 keystone2_emac_initialize(ð_priv_cfg[j]);
98 #ifdef CONFIG_SPL_BUILD
99 void spl_board_init(void)
101 spl_init_keystone_plls();
102 preloader_console_init();
105 u32 spl_boot_device(void)
107 #if defined(CONFIG_SPL_SPI_LOAD)
108 return BOOT_DEVICE_SPI;
110 puts("Unknown boot device\n");
116 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
117 int ft_board_setup(void *blob, bd_t *bd)
127 int unitrd_fixup = 0;
129 env = getenv("mem_lpae");
130 lpae = env && simple_strtol(env, NULL, 0);
131 env = getenv("uinitrd_fixup");
132 unitrd_fixup = env && simple_strtol(env, NULL, 0);
136 env = getenv("ddr3a_size");
138 ddr3a_size = simple_strtol(env, NULL, 10);
139 if ((ddr3a_size != 8) && (ddr3a_size != 4))
144 start[0] = bd->bi_dram[0].start;
145 size[0] = bd->bi_dram[0].size;
147 /* adjust memory start address for LPAE */
149 start[0] -= CONFIG_SYS_SDRAM_BASE;
150 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
153 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
154 size[1] = ((u64)ddr3a_size - 2) << 30;
155 start[1] = 0x880000000;
159 /* reserve memory at start of bank */
160 env = getenv("mem_reserve_head");
162 start[0] += ustrtoul(env, &endp, 0);
163 size[0] -= ustrtoul(env, &endp, 0);
166 env = getenv("mem_reserve");
168 size[0] -= ustrtoul(env, &endp, 0);
170 fdt_fixup_memory_banks(blob, start, size, nbanks);
172 /* Fix up the initrd */
173 if (lpae && unitrd_fixup) {
176 u64 initrd_start, initrd_end;
178 nodeoffset = fdt_path_offset(blob, "/chosen");
179 if (nodeoffset >= 0) {
180 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
181 "linux,initrd-start", NULL);
182 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
183 "linux,initrd-end", NULL);
184 if (prop1 && prop2) {
185 initrd_start = __be32_to_cpu(*prop1);
186 initrd_start -= CONFIG_SYS_SDRAM_BASE;
187 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
188 initrd_start = __cpu_to_be64(initrd_start);
189 initrd_end = __be32_to_cpu(*prop2);
190 initrd_end -= CONFIG_SYS_SDRAM_BASE;
191 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
192 initrd_end = __cpu_to_be64(initrd_end);
194 err = fdt_delprop(blob, nodeoffset,
195 "linux,initrd-start");
197 puts("error deleting initrd-start\n");
199 err = fdt_delprop(blob, nodeoffset,
202 puts("error deleting initrd-end\n");
204 err = fdt_setprop(blob, nodeoffset,
205 "linux,initrd-start",
207 sizeof(initrd_start));
209 puts("error adding initrd-start\n");
211 err = fdt_setprop(blob, nodeoffset,
216 puts("error adding linux,initrd-end\n");
224 void ft_board_setup_ex(void *blob, bd_t *bd)
231 env = getenv("mem_lpae");
232 lpae = env && simple_strtol(env, NULL, 0);
236 * the initrd and other reserved memory areas are
237 * embedded in in the DTB itslef. fix up these addresses
240 reserve_start = (u64 *)((char *)blob +
241 fdt_off_mem_rsvmap(blob));
243 *reserve_start = __cpu_to_be64(*reserve_start);
244 size = __cpu_to_be64(*(reserve_start + 1));
246 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
248 CONFIG_SYS_LPAE_SDRAM_BASE;
250 __cpu_to_be64(*reserve_start);
258 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);