git.sur5r.net Git - u-boot/blob - board/ti/ks2_evm/board_k2g.c

   1 /*
   2  * K2G EVM : Board initialization
   3  *
   4  * (C) Copyright 2015
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/ti-common/keystone_net.h>
  12 #include <asm/arch/psc_defs.h>
  13 #include <asm/arch/mmc_host_def.h>
  14 #include <fdtdec.h>
  15 #include <i2c.h>
  16 #include <remoteproc.h>
  17 #include "mux-k2g.h"
  18 #include "../common/board_detect.h"
  19
  20 #define K2G_GP_AUDIO_CODEC_ADDRESS      0x1B
  21
  22 const unsigned int sysclk_array[MAX_SYSCLK] = {
  23         19200000,
  24         24000000,
  25         25000000,
  26         26000000,
  27 };
  28
  29 unsigned int get_external_clk(u32 clk)
  30 {
  31         unsigned int clk_freq;
  32         u8 sysclk_index = get_sysclk_index();
  33
  34         switch (clk) {
  35         case sys_clk:
  36                 clk_freq = sysclk_array[sysclk_index];
  37                 break;
  38         case pa_clk:
  39                 clk_freq = sysclk_array[sysclk_index];
  40                 break;
  41         case tetris_clk:
  42                 clk_freq = sysclk_array[sysclk_index];
  43                 break;
  44         case ddr3a_clk:
  45                 clk_freq = sysclk_array[sysclk_index];
  46                 break;
  47         case uart_clk:
  48                 clk_freq = sysclk_array[sysclk_index];
  49                 break;
  50         default:
  51                 clk_freq = 0;
  52                 break;
  53         }
  54
  55         return clk_freq;
  56 }
  57
  58 static int arm_speeds[DEVSPEED_NUMSPDS] = {
  59         SPD400,
  60         SPD600,
  61         SPD800,
  62         SPD900,
  63         SPD1000,
  64         SPD900,
  65         SPD800,
  66         SPD600,
  67         SPD400,
  68         SPD200,
  69 };
  70
  71 static int dev_speeds[DEVSPEED_NUMSPDS] = {
  72         SPD600,
  73         SPD800,
  74         SPD900,
  75         SPD1000,
  76         SPD900,
  77         SPD800,
  78         SPD600,
  79         SPD400,
  80 };
  81
  82 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  83         [SYSCLK_19MHz] = {
  84                 [SPD400]        = {MAIN_PLL, 125, 3, 2},
  85                 [SPD600]        = {MAIN_PLL, 125, 2, 2},
  86                 [SPD800]        = {MAIN_PLL, 250, 3, 2},
  87                 [SPD900]        = {MAIN_PLL, 187, 2, 2},
  88                 [SPD1000]       = {MAIN_PLL, 104, 1, 2},
  89         },
  90         [SYSCLK_24MHz] = {
  91                 [SPD400]        = {MAIN_PLL, 100, 3, 2},
  92                 [SPD600]        = {MAIN_PLL, 300, 6, 2},
  93                 [SPD800]        = {MAIN_PLL, 200, 3, 2},
  94                 [SPD900]        = {MAIN_PLL, 75, 1, 2},
  95                 [SPD1000]       = {MAIN_PLL, 250, 3, 2},
  96         },
  97         [SYSCLK_25MHz] = {
  98                 [SPD400]        = {MAIN_PLL, 32, 1, 2},
  99                 [SPD600]        = {MAIN_PLL, 48, 1, 2},
 100                 [SPD800]        = {MAIN_PLL, 64, 1, 2},
 101                 [SPD900]        = {MAIN_PLL, 72, 1, 2},
 102                 [SPD1000]       = {MAIN_PLL, 80, 1, 2},
 103         },
 104         [SYSCLK_26MHz] = {
 105                 [SPD400]        = {MAIN_PLL, 400, 13, 2},
 106                 [SPD600]        = {MAIN_PLL, 230, 5, 2},
 107                 [SPD800]        = {MAIN_PLL, 123, 2, 2},
 108                 [SPD900]        = {MAIN_PLL, 69, 1, 2},
 109                 [SPD1000]       = {MAIN_PLL, 384, 5, 2},
 110         },
 111 };
 112
 113 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
 114         [SYSCLK_19MHz] = {
 115                 [SPD200]        = {TETRIS_PLL, 625, 6, 10},
 116                 [SPD400]        = {TETRIS_PLL, 125, 1, 6},
 117                 [SPD600]        = {TETRIS_PLL, 125, 1, 4},
 118                 [SPD800]        = {TETRIS_PLL, 333, 2, 4},
 119                 [SPD900]        = {TETRIS_PLL, 187, 2, 2},
 120                 [SPD1000]       = {TETRIS_PLL, 104, 1, 2},
 121         },
 122         [SYSCLK_24MHz] = {
 123                 [SPD200]        = {TETRIS_PLL, 250, 3, 10},
 124                 [SPD400]        = {TETRIS_PLL, 100, 1, 6},
 125                 [SPD600]        = {TETRIS_PLL, 100, 1, 4},
 126                 [SPD800]        = {TETRIS_PLL, 400, 3, 4},
 127                 [SPD900]        = {TETRIS_PLL, 75, 1, 2},
 128                 [SPD1000]       = {TETRIS_PLL, 250, 3, 2},
 129         },
 130         [SYSCLK_25MHz] = {
 131                 [SPD200]        = {TETRIS_PLL, 80, 1, 10},
 132                 [SPD400]        = {TETRIS_PLL, 96, 1, 6},
 133                 [SPD600]        = {TETRIS_PLL, 96, 1, 4},
 134                 [SPD800]        = {TETRIS_PLL, 128, 1, 4},
 135                 [SPD900]        = {TETRIS_PLL, 72, 1, 2},
 136                 [SPD1000]       = {TETRIS_PLL, 80, 1, 2},
 137         },
 138         [SYSCLK_26MHz] = {
 139                 [SPD200]        = {TETRIS_PLL, 307, 4, 10},
 140                 [SPD400]        = {TETRIS_PLL, 369, 4, 6},
 141                 [SPD600]        = {TETRIS_PLL, 369, 4, 4},
 142                 [SPD800]        = {TETRIS_PLL, 123, 1, 4},
 143                 [SPD900]        = {TETRIS_PLL, 69, 1, 2},
 144                 [SPD1000]       = {TETRIS_PLL, 384, 5, 2},
 145         },
 146 };
 147
 148 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
 149         [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
 150         [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
 151         [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
 152         [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
 153 };
 154
 155 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
 156         [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
 157         [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
 158         [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
 159         [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
 160 };
 161
 162 static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
 163         [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
 164         [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
 165         [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
 166         [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
 167 };
 168
 169 struct pll_init_data *get_pll_init_data(int pll)
 170 {
 171         int speed;
 172         struct pll_init_data *data = NULL;
 173         u8 sysclk_index = get_sysclk_index();
 174
 175         switch (pll) {
 176         case MAIN_PLL:
 177                 speed = get_max_dev_speed(dev_speeds);
 178                 data = &main_pll_config[sysclk_index][speed];
 179                 break;
 180         case TETRIS_PLL:
 181                 speed = get_max_arm_speed(arm_speeds);
 182                 data = &tetris_pll_config[sysclk_index][speed];
 183                 break;
 184         case NSS_PLL:
 185                 data = &nss_pll_config[sysclk_index];
 186                 break;
 187         case UART_PLL:
 188                 data = &uart_pll_config[sysclk_index];
 189                 break;
 190         case DDR3_PLL:
 191                 data = &ddr3_pll_config[sysclk_index];
 192                 break;
 193         default:
 194                 data = NULL;
 195         }
 196
 197         return data;
 198 }
 199
 200 s16 divn_val[16] = {
 201         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 202 };
 203
 204 #if defined(CONFIG_MMC)
 205 int board_mmc_init(bd_t *bis)
 206 {
 207         if (psc_enable_module(KS2_LPSC_MMC)) {
 208                 printf("%s module enabled failed\n", __func__);
 209                 return -1;
 210         }
 211
 212         if (board_is_k2g_gp())
 213                 omap_mmc_init(0, 0, 0, -1, -1);
 214
 215         omap_mmc_init(1, 0, 0, -1, -1);
 216         return 0;
 217 }
 218 #endif
 219
 220 #if defined(CONFIG_MULTI_DTB_FIT)
 221 int board_fit_config_name_match(const char *name)
 222 {
 223         bool eeprom_read = board_ti_was_eeprom_read();
 224
 225         if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
 226                 return 0;
 227         else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
 228                 return 0;
 229         else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
 230                 return 0;
 231         else
 232                 return -1;
 233 }
 234 #endif
 235
 236 #if defined(CONFIG_DTB_RESELECT)
 237 static int k2g_alt_board_detect(void)
 238 {
 239         int rc;
 240
 241         rc = i2c_set_bus_num(1);
 242         if (rc)
 243                 return rc;
 244
 245         rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
 246         if (rc)
 247                 return rc;
 248
 249         ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
 250
 251         return 0;
 252 }
 253
 254 static void k2g_reset_mux_config(void)
 255 {
 256         /* Unlock the reset mux register */
 257         clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 258
 259         /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
 260         clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
 261                         RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
 262
 263         /* lock the reset mux register to prevent any spurious writes. */
 264         setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 265 }
 266
 267 int embedded_dtb_select(void)
 268 {
 269         int rc;
 270         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 271                         CONFIG_EEPROM_CHIP_ADDRESS);
 272         if (rc) {
 273                 rc = k2g_alt_board_detect();
 274                 if (rc) {
 275                         printf("Unable to do board detection\n");
 276                         return -1;
 277                 }
 278         }
 279
 280         fdtdec_setup();
 281
 282         k2g_mux_config();
 283
 284         k2g_reset_mux_config();
 285
 286         if (board_is_k2g_gp()) {
 287                 /* deassert FLASH_HOLD */
 288                 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 289                              BIT(9));
 290                 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
 291                              BIT(9));
 292         }
 293
 294         return 0;
 295 }
 296 #endif
 297
 298 #ifdef CONFIG_BOARD_LATE_INIT
 299 int board_late_init(void)
 300 {
 301 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 302         int rc;
 303
 304         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 305                         CONFIG_EEPROM_CHIP_ADDRESS);
 306         if (rc)
 307                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 308
 309         board_ti_set_ethaddr(1);
 310 #endif
 311
 312 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 313         if (board_is_k2g_gp())
 314                 env_set("board_name", "66AK2GGP\0");
 315         else if (board_is_k2g_ice())
 316                 env_set("board_name", "66AK2GIC\0");
 317 #endif
 318         return 0;
 319 }
 320 #endif
 321
 322 #ifdef CONFIG_BOARD_EARLY_INIT_F
 323 int board_early_init_f(void)
 324 {
 325         init_plls();
 326
 327         k2g_mux_config();
 328
 329         return 0;
 330 }
 331 #endif
 332
 333 #ifdef CONFIG_SPL_BUILD
 334 void spl_init_keystone_plls(void)
 335 {
 336         init_plls();
 337 }
 338 #endif
 339
 340 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 341 struct eth_priv_t eth_priv_cfg[] = {
 342         {
 343                 .int_name       = "K2G_EMAC",
 344                 .rx_flow        = 0,
 345                 .phy_addr       = 0,
 346                 .slave_port     = 1,
 347                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 348                 .phy_if          = PHY_INTERFACE_MODE_RGMII,
 349         },
 350 };
 351
 352 int get_num_eth_ports(void)
 353 {
 354         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 355 }
 356 #endif
 357
 358 #ifdef CONFIG_TI_SECURE_DEVICE
 359 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
 360 {
 361         int id = getenv_ulong("dev_pmmc", 10, 0);
 362         int ret;
 363
 364         if (!rproc_is_initialized())
 365                 rproc_init();
 366
 367         ret = rproc_load(id, pmmc_image, pmmc_size);
 368         printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
 369                id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
 370
 371         if (!ret)
 372                 rproc_start(id);
 373 }
 374
 375 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
 376 #endif