git.sur5r.net Git - u-boot/blob - board/ti/ks2_evm/board_k2g.c

   1 /*
   2  * K2G EVM : Board initialization
   3  *
   4  * (C) Copyright 2015
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/ti-common/keystone_net.h>
  12 #include <asm/arch/psc_defs.h>
  13 #include <asm/arch/mmc_host_def.h>
  14 #include "mux-k2g.h"
  15 #include "../common/board_detect.h"
  16
  17 #define SYS_CLK         24000000
  18
  19 const unsigned int sysclk_array[MAX_SYSCLK] = {
  20         19200000,
  21         24000000,
  22         25000000,
  23         26000000,
  24 };
  25
  26 unsigned int external_clk[ext_clk_count] = {
  27         [sys_clk]       =       SYS_CLK,
  28         [pa_clk]        =       SYS_CLK,
  29         [tetris_clk]    =       SYS_CLK,
  30         [ddr3a_clk]     =       SYS_CLK,
  31         [uart_clk]      =       SYS_CLK,
  32 };
  33
  34 static int arm_speeds[DEVSPEED_NUMSPDS] = {
  35         SPD400,
  36         SPD600,
  37         SPD800,
  38         SPD900,
  39         SPD1000,
  40         SPD900,
  41         SPD800,
  42         SPD600,
  43         SPD400,
  44         SPD200,
  45 };
  46
  47 static int dev_speeds[DEVSPEED_NUMSPDS] = {
  48         SPD600,
  49         SPD800,
  50         SPD900,
  51         SPD1000,
  52         SPD900,
  53         SPD800,
  54         SPD600,
  55         SPD400,
  56 };
  57
  58 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  59         [SYSCLK_19MHz] = {
  60                 [SPD400]        = {MAIN_PLL, 125, 3, 2},
  61                 [SPD600]        = {MAIN_PLL, 125, 2, 2},
  62                 [SPD800]        = {MAIN_PLL, 250, 3, 2},
  63                 [SPD900]        = {TETRIS_PLL, 187, 2, 2},
  64                 [SPD1000]       = {TETRIS_PLL, 104, 1, 2},
  65         },
  66         [SYSCLK_24MHz] = {
  67                 [SPD400]        = {MAIN_PLL, 100, 3, 2},
  68                 [SPD600]        = {MAIN_PLL, 300, 6, 2},
  69                 [SPD800]        = {MAIN_PLL, 200, 3, 2},
  70                 [SPD900]        = {TETRIS_PLL, 75, 1, 2},
  71                 [SPD1000]       = {TETRIS_PLL, 250, 3, 2},
  72         },
  73         [SYSCLK_25MHz] = {
  74                 [SPD400]        = {MAIN_PLL, 32, 1, 2},
  75                 [SPD600]        = {MAIN_PLL, 48, 1, 2},
  76                 [SPD800]        = {MAIN_PLL, 64, 1, 2},
  77                 [SPD900]        = {TETRIS_PLL, 72, 1, 2},
  78                 [SPD1000]       = {TETRIS_PLL, 80, 1, 2},
  79         },
  80         [SYSCLK_26MHz] = {
  81                 [SPD400]        = {MAIN_PLL, 400, 13, 2},
  82                 [SPD600]        = {MAIN_PLL, 230, 5, 2},
  83                 [SPD800]        = {MAIN_PLL, 123, 2, 2},
  84                 [SPD900]        = {TETRIS_PLL, 69, 1, 2},
  85                 [SPD1000]       = {TETRIS_PLL, 384, 5, 2},
  86         },
  87 };
  88
  89 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  90         [SYSCLK_19MHz] = {
  91                 [SPD200]        = {TETRIS_PLL, 625, 6, 10},
  92                 [SPD400]        = {TETRIS_PLL, 125, 1, 6},
  93                 [SPD600]        = {TETRIS_PLL, 125, 1, 4},
  94                 [SPD800]        = {TETRIS_PLL, 333, 2, 4},
  95                 [SPD900]        = {TETRIS_PLL, 187, 2, 2},
  96                 [SPD1000]       = {TETRIS_PLL, 104, 1, 2},
  97         },
  98         [SYSCLK_24MHz] = {
  99                 [SPD200]        = {TETRIS_PLL, 250, 3, 10},
 100                 [SPD400]        = {TETRIS_PLL, 100, 1, 6},
 101                 [SPD600]        = {TETRIS_PLL, 100, 1, 4},
 102                 [SPD800]        = {TETRIS_PLL, 400, 3, 4},
 103                 [SPD900]        = {TETRIS_PLL, 75, 1, 2},
 104                 [SPD1000]       = {TETRIS_PLL, 250, 3, 2},
 105         },
 106         [SYSCLK_25MHz] = {
 107                 [SPD200]        = {TETRIS_PLL, 80, 1, 10},
 108                 [SPD400]        = {TETRIS_PLL, 96, 1, 6},
 109                 [SPD600]        = {TETRIS_PLL, 96, 1, 4},
 110                 [SPD800]        = {TETRIS_PLL, 128, 1, 4},
 111                 [SPD900]        = {TETRIS_PLL, 72, 1, 2},
 112                 [SPD1000]       = {TETRIS_PLL, 80, 1, 2},
 113         },
 114         [SYSCLK_26MHz] = {
 115                 [SPD200]        = {TETRIS_PLL, 307, 4, 10},
 116                 [SPD400]        = {TETRIS_PLL, 369, 4, 6},
 117                 [SPD600]        = {TETRIS_PLL, 369, 4, 4},
 118                 [SPD800]        = {TETRIS_PLL, 123, 1, 4},
 119                 [SPD900]        = {TETRIS_PLL, 69, 1, 2},
 120                 [SPD1000]       = {TETRIS_PLL, 384, 5, 2},
 121         },
 122 };
 123
 124 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
 125         [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
 126         [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
 127         [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
 128         [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
 129 };
 130
 131 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
 132         [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
 133         [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
 134         [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
 135         [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
 136 };
 137
 138 static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
 139         [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
 140         [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
 141         [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
 142         [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
 143 };
 144
 145 struct pll_init_data *get_pll_init_data(int pll)
 146 {
 147         int speed;
 148         struct pll_init_data *data = NULL;
 149         u8 sysclk_index = get_sysclk_index();
 150
 151         switch (pll) {
 152         case MAIN_PLL:
 153                 speed = get_max_dev_speed(dev_speeds);
 154                 data = &main_pll_config[sysclk_index][speed];
 155                 break;
 156         case TETRIS_PLL:
 157                 speed = get_max_arm_speed(arm_speeds);
 158                 data = &tetris_pll_config[sysclk_index][speed];
 159                 break;
 160         case NSS_PLL:
 161                 data = &nss_pll_config[sysclk_index];
 162                 break;
 163         case UART_PLL:
 164                 data = &uart_pll_config[sysclk_index];
 165                 break;
 166         case DDR3_PLL:
 167                 data = &ddr3_pll_config[sysclk_index];
 168                 break;
 169         default:
 170                 data = NULL;
 171         }
 172
 173         return data;
 174 }
 175
 176 s16 divn_val[16] = {
 177         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 178 };
 179
 180 #if defined(CONFIG_GENERIC_MMC)
 181 int board_mmc_init(bd_t *bis)
 182 {
 183         if (psc_enable_module(KS2_LPSC_MMC)) {
 184                 printf("%s module enabled failed\n", __func__);
 185                 return -1;
 186         }
 187
 188         omap_mmc_init(0, 0, 0, -1, -1);
 189         omap_mmc_init(1, 0, 0, -1, -1);
 190         return 0;
 191 }
 192 #endif
 193
 194 #ifdef CONFIG_BOARD_EARLY_INIT_F
 195
 196 static void k2g_reset_mux_config(void)
 197 {
 198         /* Unlock the reset mux register */
 199         clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 200
 201         /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
 202         clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
 203                         RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
 204
 205         /* lock the reset mux register to prevent any spurious writes. */
 206         setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 207 }
 208
 209 int board_early_init_f(void)
 210 {
 211         init_plls();
 212
 213         k2g_mux_config();
 214
 215         k2g_reset_mux_config();
 216
 217         /* deassert FLASH_HOLD */
 218         clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 219                      BIT(9));
 220         setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
 221                      BIT(9));
 222
 223         return 0;
 224 }
 225 #endif
 226
 227 #ifdef CONFIG_BOARD_LATE_INIT
 228 int board_late_init(void)
 229 {
 230 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 231         int rc;
 232
 233         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 234                         CONFIG_EEPROM_CHIP_ADDRESS);
 235         if (rc)
 236                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 237
 238         board_ti_set_ethaddr(1);
 239 #endif
 240
 241         return 0;
 242 }
 243 #endif
 244
 245 #ifdef CONFIG_SPL_BUILD
 246 void spl_init_keystone_plls(void)
 247 {
 248         init_plls();
 249 }
 250 #endif
 251
 252 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 253 struct eth_priv_t eth_priv_cfg[] = {
 254         {
 255                 .int_name       = "K2G_EMAC",
 256                 .rx_flow        = 0,
 257                 .phy_addr       = 0,
 258                 .slave_port     = 1,
 259                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 260                 .phy_if          = PHY_INTERFACE_MODE_RGMII,
 261         },
 262 };
 263
 264 int get_num_eth_ports(void)
 265 {
 266         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 267 }
 268 #endif