2 * K2G EVM : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/ti-common/keystone_net.h>
12 #include <asm/arch/psc_defs.h>
13 #include <asm/arch/mmc_host_def.h>
17 #include "../common/board_detect.h"
19 #define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
21 const unsigned int sysclk_array[MAX_SYSCLK] = {
28 unsigned int get_external_clk(u32 clk)
30 unsigned int clk_freq;
31 u8 sysclk_index = get_sysclk_index();
35 clk_freq = sysclk_array[sysclk_index];
38 clk_freq = sysclk_array[sysclk_index];
41 clk_freq = sysclk_array[sysclk_index];
44 clk_freq = sysclk_array[sysclk_index];
47 clk_freq = sysclk_array[sysclk_index];
57 static int arm_speeds[DEVSPEED_NUMSPDS] = {
70 static int dev_speeds[DEVSPEED_NUMSPDS] = {
81 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
83 [SPD400] = {MAIN_PLL, 125, 3, 2},
84 [SPD600] = {MAIN_PLL, 125, 2, 2},
85 [SPD800] = {MAIN_PLL, 250, 3, 2},
86 [SPD900] = {MAIN_PLL, 187, 2, 2},
87 [SPD1000] = {MAIN_PLL, 104, 1, 2},
90 [SPD400] = {MAIN_PLL, 100, 3, 2},
91 [SPD600] = {MAIN_PLL, 300, 6, 2},
92 [SPD800] = {MAIN_PLL, 200, 3, 2},
93 [SPD900] = {MAIN_PLL, 75, 1, 2},
94 [SPD1000] = {MAIN_PLL, 250, 3, 2},
97 [SPD400] = {MAIN_PLL, 32, 1, 2},
98 [SPD600] = {MAIN_PLL, 48, 1, 2},
99 [SPD800] = {MAIN_PLL, 64, 1, 2},
100 [SPD900] = {MAIN_PLL, 72, 1, 2},
101 [SPD1000] = {MAIN_PLL, 80, 1, 2},
104 [SPD400] = {MAIN_PLL, 400, 13, 2},
105 [SPD600] = {MAIN_PLL, 230, 5, 2},
106 [SPD800] = {MAIN_PLL, 123, 2, 2},
107 [SPD900] = {MAIN_PLL, 69, 1, 2},
108 [SPD1000] = {MAIN_PLL, 384, 5, 2},
112 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
114 [SPD200] = {TETRIS_PLL, 625, 6, 10},
115 [SPD400] = {TETRIS_PLL, 125, 1, 6},
116 [SPD600] = {TETRIS_PLL, 125, 1, 4},
117 [SPD800] = {TETRIS_PLL, 333, 2, 4},
118 [SPD900] = {TETRIS_PLL, 187, 2, 2},
119 [SPD1000] = {TETRIS_PLL, 104, 1, 2},
122 [SPD200] = {TETRIS_PLL, 250, 3, 10},
123 [SPD400] = {TETRIS_PLL, 100, 1, 6},
124 [SPD600] = {TETRIS_PLL, 100, 1, 4},
125 [SPD800] = {TETRIS_PLL, 400, 3, 4},
126 [SPD900] = {TETRIS_PLL, 75, 1, 2},
127 [SPD1000] = {TETRIS_PLL, 250, 3, 2},
130 [SPD200] = {TETRIS_PLL, 80, 1, 10},
131 [SPD400] = {TETRIS_PLL, 96, 1, 6},
132 [SPD600] = {TETRIS_PLL, 96, 1, 4},
133 [SPD800] = {TETRIS_PLL, 128, 1, 4},
134 [SPD900] = {TETRIS_PLL, 72, 1, 2},
135 [SPD1000] = {TETRIS_PLL, 80, 1, 2},
138 [SPD200] = {TETRIS_PLL, 307, 4, 10},
139 [SPD400] = {TETRIS_PLL, 369, 4, 6},
140 [SPD600] = {TETRIS_PLL, 369, 4, 4},
141 [SPD800] = {TETRIS_PLL, 123, 1, 4},
142 [SPD900] = {TETRIS_PLL, 69, 1, 2},
143 [SPD1000] = {TETRIS_PLL, 384, 5, 2},
147 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
148 [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
149 [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
150 [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
151 [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
154 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
155 [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
156 [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
157 [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
158 [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
161 static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
162 [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
163 [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
164 [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
165 [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
168 struct pll_init_data *get_pll_init_data(int pll)
171 struct pll_init_data *data = NULL;
172 u8 sysclk_index = get_sysclk_index();
176 speed = get_max_dev_speed(dev_speeds);
177 data = &main_pll_config[sysclk_index][speed];
180 speed = get_max_arm_speed(arm_speeds);
181 data = &tetris_pll_config[sysclk_index][speed];
184 data = &nss_pll_config[sysclk_index];
187 data = &uart_pll_config[sysclk_index];
190 data = &ddr3_pll_config[sysclk_index];
200 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
203 #if defined(CONFIG_MMC)
204 int board_mmc_init(bd_t *bis)
206 if (psc_enable_module(KS2_LPSC_MMC)) {
207 printf("%s module enabled failed\n", __func__);
211 omap_mmc_init(0, 0, 0, -1, -1);
212 omap_mmc_init(1, 0, 0, -1, -1);
217 #if defined(CONFIG_FIT_EMBED)
218 int board_fit_config_name_match(const char *name)
220 bool eeprom_read = board_ti_was_eeprom_read();
222 if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
224 else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
231 #if defined(CONFIG_DTB_RESELECT)
232 static int k2g_alt_board_detect(void)
236 rc = i2c_set_bus_num(1);
240 rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
244 ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
249 static void k2g_reset_mux_config(void)
251 /* Unlock the reset mux register */
252 clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
254 /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
255 clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
256 RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
258 /* lock the reset mux register to prevent any spurious writes. */
259 setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
262 int embedded_dtb_select(void)
265 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
266 CONFIG_EEPROM_CHIP_ADDRESS);
268 rc = k2g_alt_board_detect();
270 printf("Unable to do board detection\n");
279 k2g_reset_mux_config();
281 /* deassert FLASH_HOLD */
282 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
284 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
291 #ifdef CONFIG_BOARD_LATE_INIT
292 int board_late_init(void)
294 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
297 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
298 CONFIG_EEPROM_CHIP_ADDRESS);
300 printf("ti_i2c_eeprom_init failed %d\n", rc);
302 board_ti_set_ethaddr(1);
309 #ifdef CONFIG_BOARD_EARLY_INIT_F
310 int board_early_init_f(void)
320 #ifdef CONFIG_SPL_BUILD
321 void spl_init_keystone_plls(void)
327 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
328 struct eth_priv_t eth_priv_cfg[] = {
330 .int_name = "K2G_EMAC",
334 .sgmii_link_type = SGMII_LINK_MAC_PHY,
335 .phy_if = PHY_INTERFACE_MODE_RGMII,
339 int get_num_eth_ports(void)
341 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);