git.sur5r.net Git - u-boot/blob - board/ti/ks2_evm/ddr3_k2e.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2014-2015
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include "ddr3_cfg.h"
  12 #include <asm/arch/ddr3.h>
  13
  14 static struct pll_init_data ddr3_400 = DDR3_PLL_400;
  15 static struct pll_init_data ddr3_333 = DDR3_PLL_333;
  16
  17 u32 ddr3_init(void)
  18 {
  19         struct ddr3_spd_cb spd_cb;
  20
  21         if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
  22                 printf("Sorry, I don't know how to configure DDR3A.\n"
  23                        "Bye :(\n");
  24                 for (;;)
  25                         ;
  26         }
  27
  28         printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
  29
  30         printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
  31         if (spd_cb.ddrspdclock == 1600)
  32                 init_pll(&ddr3_400);
  33         else
  34                 init_pll(&ddr3_333);
  35
  36         /* Reset DDR3 PHY after PLL enabled */
  37         ddr3_reset_ddrphy();
  38
  39         spd_cb.phy_cfg.zq0cr1 |= 0x10000;
  40         spd_cb.phy_cfg.zq1cr1 |= 0x10000;
  41         spd_cb.phy_cfg.zq2cr1 |= 0x10000;
  42         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
  43         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
  44
  45         printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
  46
  47         return (u32)spd_cb.ddr_size_gbyte;
  48 }