git.sur5r.net Git - u-boot/blob - board/ti/ks2_evm/ddr3_k2g.c

   1 /*
   2  * K2G: DDR3 initialization
   3  *
   4  * (C) Copyright 2015
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include "ddr3_cfg.h"
  12 #include <asm/arch/ddr3.h>
  13 #include "board.h"
  14
  15 /* K2G GP EVM DDR3 Configuration */
  16 struct ddr3_phy_config ddr3phy_800_2g = {
  17         .pllcr          = 0x000DC000ul,
  18         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
  19         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
  20         .ptr0           = 0x42C21590ul,
  21         .ptr1           = 0xD05612C0ul,
  22         .ptr2           = 0,
  23         .ptr3           = 0x06C30D40ul,
  24         .ptr4           = 0x06413880ul,
  25         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
  26         .dcr_val        = ((1 << 10)),
  27         .dtpr0          = 0x550F6644ul,
  28         .dtpr1          = 0x328341E0ul,
  29         .dtpr2          = 0x50022A00ul,
  30         .mr0            = 0x00001430ul,
  31         .mr1            = 0x00000006ul,
  32         .mr2            = 0x00000000ul,
  33         .dtcr           = 0x710035C7ul,
  34         .pgcr2          = 0x00F03D09ul,
  35         .zq0cr1         = 0x0001005Dul,
  36         .zq1cr1         = 0x0001005Bul,
  37         .zq2cr1         = 0x0001005Bul,
  38         .pir_v1         = 0x00000033ul,
  39         .datx8_2_mask   = 0,
  40         .datx8_2_val    = 0,
  41         .datx8_3_mask   = 0,
  42         .datx8_3_val    = 0,
  43         .datx8_4_mask   = 0,
  44         .datx8_4_val    = ((1 << 0)),
  45         .datx8_5_mask   = DXEN_MASK,
  46         .datx8_5_val    = 0,
  47         .datx8_6_mask   = DXEN_MASK,
  48         .datx8_6_val    = 0,
  49         .datx8_7_mask   = DXEN_MASK,
  50         .datx8_7_val    = 0,
  51         .datx8_8_mask   = DXEN_MASK,
  52         .datx8_8_val    = 0,
  53         .pir_v2         = 0x00000F81ul,
  54 };
  55
  56 struct ddr3_emif_config ddr3_800_2g = {
  57         .sdcfg          = 0x62005662ul,
  58         .sdtim1         = 0x0A385033ul,
  59         .sdtim2         = 0x00001CA5ul,
  60         .sdtim3         = 0x21ADFF32ul,
  61         .sdtim4         = 0x533F067Ful,
  62         .zqcfg          = 0x70073200ul,
  63         .sdrfc          = 0x00000C34ul,
  64 };
  65
  66 /* K2G ICE evm DDR3 Configuration */
  67 struct ddr3_phy_config ddr3phy_800_512mb = {
  68         .pllcr          = 0x000DC000ul,
  69         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
  70         .pgcr1_val      = ((1 << 2) | (2 << 7) | (1 << 23)),
  71         .ptr0           = 0x42C21590ul,
  72         .ptr1           = 0xD05612C0ul,
  73         .ptr2           = 0,
  74         .ptr3           = 0x06C30D40ul,
  75         .ptr4           = 0x06413880ul,
  76         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
  77         .dcr_val        = ((1 << 10)),
  78         .dtpr0          = 0x550E6644ul,
  79         .dtpr1          = 0x32834200ul,
  80         .dtpr2          = 0x50022A00ul,
  81         .mr0            = 0x00001430ul,
  82         .mr1            = 0x00000006ul,
  83         .mr2            = 0x00000008ul,
  84         .dtcr           = 0x710035C7ul,
  85         .pgcr2          = 0x00F03D09ul,
  86         .zq0cr1         = 0x0001005Dul,
  87         .zq1cr1         = 0x0001005Bul,
  88         .zq2cr1         = 0x0001005Bul,
  89         .pir_v1         = 0x00000033ul,
  90         .datx8_2_mask   = DXEN_MASK,
  91         .datx8_2_val    = 0,
  92         .datx8_3_mask   = DXEN_MASK,
  93         .datx8_3_val    = 0,
  94         .datx8_4_mask   = DXEN_MASK,
  95         .datx8_4_val    = 0,
  96         .datx8_5_mask   = DXEN_MASK,
  97         .datx8_5_val    = 0,
  98         .datx8_6_mask   = DXEN_MASK,
  99         .datx8_6_val    = 0,
 100         .datx8_7_mask   = DXEN_MASK,
 101         .datx8_7_val    = 0,
 102         .datx8_8_mask   = DXEN_MASK,
 103         .datx8_8_val    = 0,
 104         .pir_v2         = 0x00000F81ul,
 105 };
 106
 107 struct ddr3_emif_config ddr3_800_512mb = {
 108         .sdcfg          = 0x62006662ul,
 109         .sdtim1         = 0x0A385033ul,
 110         .sdtim2         = 0x00001CA5ul,
 111         .sdtim3         = 0x21ADFF32ul,
 112         .sdtim4         = 0x533F067Ful,
 113         .zqcfg          = 0x70073200ul,
 114         .sdrfc          = 0x00000C34ul,
 115 };
 116
 117 u32 ddr3_init(void)
 118 {
 119         /* Reset DDR3 PHY after PLL enabled */
 120         ddr3_reset_ddrphy();
 121
 122         if (board_is_k2g_gp()) {
 123                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
 124                 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
 125         } else if (board_is_k2g_ice()) {
 126                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
 127                 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
 128         }
 129
 130         return 0;
 131 }
 132
 133 inline int ddr3_get_size(void)
 134 {
 135         return 2;
 136 }