git.sur5r.net Git - u-boot/blob - board/ti/ks2_evm/ddr3_k2g.c

   1 /*
   2  * K2G: DDR3 initialization
   3  *
   4  * (C) Copyright 2015
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include "ddr3_cfg.h"
  12 #include <asm/arch/ddr3.h>
  13
  14 struct ddr3_phy_config ddr3phy_800_2g = {
  15         .pllcr          = 0x000DC000ul,
  16         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
  17         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
  18         .ptr0           = 0x42C21590ul,
  19         .ptr1           = 0xD05612C0ul,
  20         .ptr2           = 0,
  21         .ptr3           = 0x06C30D40ul,
  22         .ptr4           = 0x06413880ul,
  23         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
  24         .dcr_val        = ((1 << 10)),
  25         .dtpr0          = 0x550F6644ul,
  26         .dtpr1          = 0x328341E0ul,
  27         .dtpr2          = 0x50022A00ul,
  28         .mr0            = 0x00001430ul,
  29         .mr1            = 0x00000006ul,
  30         .mr2            = 0x00000000ul,
  31         .dtcr           = 0x710035C7ul,
  32         .pgcr2          = 0x00F03D09ul,
  33         .zq0cr1         = 0x0001005Dul,
  34         .zq1cr1         = 0x0001005Bul,
  35         .zq2cr1         = 0x0001005Bul,
  36         .pir_v1         = 0x00000033ul,
  37         .datx8_2_mask   = 0,
  38         .datx8_2_val    = 0,
  39         .datx8_3_mask   = 0,
  40         .datx8_3_val    = 0,
  41         .datx8_4_mask   = 0,
  42         .datx8_4_val    = ((1 << 0)),
  43         .datx8_5_mask   = DXEN_MASK,
  44         .datx8_5_val    = 0,
  45         .datx8_6_mask   = DXEN_MASK,
  46         .datx8_6_val    = 0,
  47         .datx8_7_mask   = DXEN_MASK,
  48         .datx8_7_val    = 0,
  49         .datx8_8_mask   = DXEN_MASK,
  50         .datx8_8_val    = 0,
  51         .pir_v2         = 0x00000F81ul,
  52 };
  53
  54 struct ddr3_emif_config ddr3_800_2g = {
  55         .sdcfg          = 0x62005662ul,
  56         .sdtim1         = 0x0A385033ul,
  57         .sdtim2         = 0x00001CA5ul,
  58         .sdtim3         = 0x21ADFF32ul,
  59         .sdtim4         = 0x533F067Ful,
  60         .zqcfg          = 0x70073200ul,
  61         .sdrfc          = 0x00000C34ul,
  62 };
  63
  64 u32 ddr3_init(void)
  65 {
  66         /* Reset DDR3 PHY after PLL enabled */
  67         ddr3_reset_ddrphy();
  68
  69         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
  70         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
  71
  72         return 0;
  73 }
  74
  75 inline int ddr3_get_size(void)
  76 {
  77         return 2;
  78 }