git.sur5r.net Git - u-boot/blob - board/ti/ks2_evm/ddr3_k2hk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone2: DDR3 initialization
   4  *
   5  * (C) Copyright 2012-2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include "ddr3_cfg.h"
  11 #include <asm/arch/ddr3.h>
  12 #include <asm/arch/hardware.h>
  13
  14 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
  15 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
  16
  17 u32 ddr3_init(void)
  18 {
  19         u32 ddr3_size;
  20         struct ddr3_spd_cb spd_cb;
  21
  22         if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
  23                 printf("Sorry, I don't know how to configure DDR3A.\n"
  24                        "Bye :(\n");
  25                 for (;;)
  26                         ;
  27         }
  28
  29         printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
  30
  31         if ((cpu_revision() > 1) ||
  32             (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
  33                 printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
  34                 if (spd_cb.ddrspdclock == 1600)
  35                         init_pll(&ddr3a_400);
  36                 else
  37                         init_pll(&ddr3a_333);
  38         }
  39
  40         if (cpu_revision() > 0) {
  41                 if (cpu_revision() > 1) {
  42                         /* PG 2.0 */
  43                         /* Reset DDR3A PHY after PLL enabled */
  44                         ddr3_reset_ddrphy();
  45                         spd_cb.phy_cfg.zq0cr1 |= 0x10000;
  46                         spd_cb.phy_cfg.zq1cr1 |= 0x10000;
  47                         spd_cb.phy_cfg.zq2cr1 |= 0x10000;
  48                 }
  49                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
  50
  51                 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
  52
  53                 ddr3_size = spd_cb.ddr_size_gbyte;
  54         } else {
  55                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
  56                 spd_cb.emif_cfg.sdcfg |= 0x1000;
  57                 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
  58                 ddr3_size = spd_cb.ddr_size_gbyte / 2;
  59         }
  60         printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
  61
  62         /* Apply the workaround for PG 1.0 and 1.1 Silicons */
  63         if (cpu_revision() <= 1)
  64                 ddr3_err_reset_workaround();
  65
  66         return ddr3_size;
  67 }