2 * Keystone2: DDR3 initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/ddr3.h>
13 #include <asm/arch/hardware.h>
17 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
18 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
24 ddr3_get_dimm_params(dimm_name);
26 printf("Detected SO-DIMM [%s]\n", dimm_name);
28 if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
30 if (cpu_revision() > 0) {
31 if (cpu_revision() > 1) {
33 /* Reset DDR3A PHY after PLL enabled */
35 ddr3phy_1600_8g.zq0cr1 |= 0x10000;
36 ddr3phy_1600_8g.zq1cr1 |= 0x10000;
37 ddr3phy_1600_8g.zq2cr1 |= 0x10000;
38 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
42 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
46 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
48 printf("DRAM: Capacity 8 GiB (includes reported below)\n");
51 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
52 ddr3_1600_8g.sdcfg |= 0x1000;
53 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
55 printf("DRAM: Capacity 4 GiB (includes reported below)\n");
58 } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
60 if (cpu_revision() > 0) {
61 if (cpu_revision() > 1) {
63 /* Reset DDR3A PHY after PLL enabled */
65 ddr3phy_1333_2g.zq0cr1 |= 0x10000;
66 ddr3phy_1333_2g.zq1cr1 |= 0x10000;
67 ddr3phy_1333_2g.zq2cr1 |= 0x10000;
68 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
72 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
75 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
78 printf("DRAM: 2 GiB");
80 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
81 ddr3_1333_2g.sdcfg |= 0x1000;
82 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
85 printf("DRAM: 1 GiB");
88 printf("Unknown SO-DIMM. Cannot configure DDR3\n");
93 /* Apply the workaround for PG 1.0 and 1.1 Silicons */
94 if (cpu_revision() <= 1)
95 ddr3_err_reset_workaround();
99 * ddr3_get_size - return ddr3 size in GiB
101 int ddr3_get_size(void)