2 * Keystone2: DDR3 initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/ddr3.h>
13 #include <asm/arch/hardware.h>
15 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
16 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
22 ddr3_get_dimm_params(dimm_name);
24 printf("Detected SO-DIMM [%s]\n", dimm_name);
26 if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
28 if (cpu_revision() > 0) {
29 if (cpu_revision() > 1) {
31 /* Reset DDR3A PHY after PLL enabled */
33 ddr3phy_1600_8g.zq0cr1 |= 0x10000;
34 ddr3phy_1600_8g.zq1cr1 |= 0x10000;
35 ddr3phy_1600_8g.zq2cr1 |= 0x10000;
36 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
40 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
44 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
46 printf("DRAM: Capacity 8 GiB (includes reported below)\n");
48 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
49 ddr3_1600_8g.sdcfg |= 0x1000;
50 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
52 printf("DRAM: Capacity 4 GiB (includes reported below)\n");
54 } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
56 if (cpu_revision() > 0) {
57 if (cpu_revision() > 1) {
59 /* Reset DDR3A PHY after PLL enabled */
61 ddr3phy_1333_2g.zq0cr1 |= 0x10000;
62 ddr3phy_1333_2g.zq1cr1 |= 0x10000;
63 ddr3phy_1333_2g.zq2cr1 |= 0x10000;
64 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
68 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
71 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
74 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
75 ddr3_1333_2g.sdcfg |= 0x1000;
76 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
80 printf("Unknown SO-DIMM. Cannot configure DDR3\n");