2 * Keystone2: DDR3 initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/ddr3.h>
13 #include <asm/arch/hardware.h>
15 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
16 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
23 ddr3_get_dimm_params(dimm_name);
25 printf("Detected SO-DIMM [%s]\n", dimm_name);
27 if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
29 if (cpu_revision() > 0) {
30 if (cpu_revision() > 1) {
32 /* Reset DDR3A PHY after PLL enabled */
34 ddr3phy_1600_8g.zq0cr1 |= 0x10000;
35 ddr3phy_1600_8g.zq1cr1 |= 0x10000;
36 ddr3phy_1600_8g.zq2cr1 |= 0x10000;
37 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
41 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
45 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
47 printf("DRAM: Capacity 8 GiB (includes reported below)\n");
50 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
51 ddr3_1600_8g.sdcfg |= 0x1000;
52 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
54 printf("DRAM: Capacity 4 GiB (includes reported below)\n");
57 } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
59 if (cpu_revision() > 0) {
60 if (cpu_revision() > 1) {
62 /* Reset DDR3A PHY after PLL enabled */
64 ddr3phy_1333_2g.zq0cr1 |= 0x10000;
65 ddr3phy_1333_2g.zq1cr1 |= 0x10000;
66 ddr3phy_1333_2g.zq2cr1 |= 0x10000;
67 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
71 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
74 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
77 printf("DRAM: 2 GiB");
79 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
80 ddr3_1333_2g.sdcfg |= 0x1000;
81 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
84 printf("DRAM: 1 GiB");
87 printf("Unknown SO-DIMM. Cannot configure DDR3\n");
92 /* Apply the workaround for PG 1.0 and 1.1 Silicons */
93 if (cpu_revision() <= 1)
94 ddr3_err_reset_workaround();