git.sur5r.net Git - u-boot/blob - board/ti/ks2_evm/ddr3_k2hk.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/ddr3.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/io.h>
  14 #include <i2c.h>
  15
  16 /************************* *****************************/
  17 static struct ddr3_phy_config ddr3phy_1600_64A = {
  18         .pllcr          = 0x0001C000ul,
  19         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
  20         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
  21         .ptr0           = 0x42C21590ul,
  22         .ptr1           = 0xD05612C0ul,
  23         .ptr2           = 0, /* not set in gel */
  24         .ptr3           = 0x0D861A80ul,
  25         .ptr4           = 0x0C827100ul,
  26         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
  27         .dcr_val        = ((1 << 10) | (1 << 27)),
  28         .dtpr0          = 0xA19DBB66ul,
  29         .dtpr1          = 0x12868300ul,
  30         .dtpr2          = 0x50035200ul,
  31         .mr0            = 0x00001C70ul,
  32         .mr1            = 0x00000006ul,
  33         .mr2            = 0x00000018ul,
  34         .dtcr           = 0x730035C7ul,
  35         .pgcr2          = 0x00F07A12ul,
  36         .zq0cr1         = 0x0000005Dul,
  37         .zq1cr1         = 0x0000005Bul,
  38         .zq2cr1         = 0x0000005Bul,
  39         .pir_v1         = 0x00000033ul,
  40         .pir_v2         = 0x0000FF81ul,
  41 };
  42
  43 static struct ddr3_emif_config ddr3_1600_64 = {
  44         .sdcfg          = 0x6200CE6aul,
  45         .sdtim1         = 0x16709C55ul,
  46         .sdtim2         = 0x00001D4Aul,
  47         .sdtim3         = 0x435DFF54ul,
  48         .sdtim4         = 0x553F0CFFul,
  49         .zqcfg          = 0xF0073200ul,
  50         .sdrfc          = 0x00001869ul,
  51 };
  52
  53 static struct ddr3_phy_config ddr3phy_1600_32 = {
  54         .pllcr          = 0x0001C000ul,
  55         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
  56         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
  57         .ptr0           = 0x42C21590ul,
  58         .ptr1           = 0xD05612C0ul,
  59         .ptr2           = 0, /* not set in gel */
  60         .ptr3           = 0x0D861A80ul,
  61         .ptr4           = 0x0C827100ul,
  62         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
  63         .dcr_val        = ((1 << 10) | (1 << 27)),
  64         .dtpr0          = 0xA19DBB66ul,
  65         .dtpr1          = 0x12868300ul,
  66         .dtpr2          = 0x50035200ul,
  67         .mr0            = 0x00001C70ul,
  68         .mr1            = 0x00000006ul,
  69         .mr2            = 0x00000018ul,
  70         .dtcr           = 0x730035C7ul,
  71         .pgcr2          = 0x00F07A12ul,
  72         .zq0cr1         = 0x0000005Dul,
  73         .zq1cr1         = 0x0000005Bul,
  74         .zq2cr1         = 0x0000005Bul,
  75         .pir_v1         = 0x00000033ul,
  76         .pir_v2         = 0x0000FF81ul,
  77 };
  78
  79 static struct ddr3_emif_config ddr3_1600_32 = {
  80         .sdcfg          = 0x6200DE6aul,
  81         .sdtim1         = 0x16709C55ul,
  82         .sdtim2         = 0x00001D4Aul,
  83         .sdtim3         = 0x435DFF54ul,
  84         .sdtim4         = 0x553F0CFFul,
  85         .zqcfg          = 0x70073200ul,
  86         .sdrfc          = 0x00001869ul,
  87 };
  88
  89 /************************* *****************************/
  90 static struct ddr3_phy_config ddr3phy_1333_64A = {
  91         .pllcr          = 0x0005C000ul,
  92         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
  93         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
  94         .ptr0           = 0x42C21590ul,
  95         .ptr1           = 0xD05612C0ul,
  96         .ptr2           = 0, /* not set in gel */
  97         .ptr3           = 0x0B4515C2ul,
  98         .ptr4           = 0x0A6E08B4ul,
  99         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
 100                            NOSRA_MASK | UDIMM_MASK),
 101         .dcr_val        = ((1 << 10) | (1 << 27) | (1 << 29)),
 102         .dtpr0          = 0x8558AA55ul,
 103         .dtpr1          = 0x12857280ul,
 104         .dtpr2          = 0x5002C200ul,
 105         .mr0            = 0x00001A60ul,
 106         .mr1            = 0x00000006ul,
 107         .mr2            = 0x00000010ul,
 108         .dtcr           = 0x710035C7ul,
 109         .pgcr2          = 0x00F065B8ul,
 110         .zq0cr1         = 0x0000005Dul,
 111         .zq1cr1         = 0x0000005Bul,
 112         .zq2cr1         = 0x0000005Bul,
 113         .pir_v1         = 0x00000033ul,
 114         .pir_v2         = 0x0000FF81ul,
 115 };
 116
 117 static struct ddr3_emif_config ddr3_1333_64 = {
 118         .sdcfg          = 0x62008C62ul,
 119         .sdtim1         = 0x125C8044ul,
 120         .sdtim2         = 0x00001D29ul,
 121         .sdtim3         = 0x32CDFF43ul,
 122         .sdtim4         = 0x543F0ADFul,
 123         .zqcfg          = 0xF0073200ul,
 124         .sdrfc          = 0x00001457ul,
 125 };
 126
 127 static struct ddr3_phy_config ddr3phy_1333_32 = {
 128         .pllcr          = 0x0005C000ul,
 129         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
 130         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
 131         .ptr0           = 0x42C21590ul,
 132         .ptr1           = 0xD05612C0ul,
 133         .ptr2           = 0, /* not set in gel */
 134         .ptr3           = 0x0B4515C2ul,
 135         .ptr4           = 0x0A6E08B4ul,
 136         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
 137                            NOSRA_MASK | UDIMM_MASK),
 138         .dcr_val        = ((1 << 10) | (1 << 27) | (1 << 29)),
 139         .dtpr0          = 0x8558AA55ul,
 140         .dtpr1          = 0x12857280ul,
 141         .dtpr2          = 0x5002C200ul,
 142         .mr0            = 0x00001A60ul,
 143         .mr1            = 0x00000006ul,
 144         .mr2            = 0x00000010ul,
 145         .dtcr           = 0x710035C7ul,
 146         .pgcr2          = 0x00F065B8ul,
 147         .zq0cr1         = 0x0000005Dul,
 148         .zq1cr1         = 0x0000005Bul,
 149         .zq2cr1         = 0x0000005Bul,
 150         .pir_v1         = 0x00000033ul,
 151         .pir_v2         = 0x0000FF81ul,
 152 };
 153
 154 static struct ddr3_emif_config ddr3_1333_32 = {
 155         .sdcfg          = 0x62009C62ul,
 156         .sdtim1         = 0x125C8044ul,
 157         .sdtim2         = 0x00001D29ul,
 158         .sdtim3         = 0x32CDFF43ul,
 159         .sdtim4         = 0x543F0ADFul,
 160         .zqcfg          = 0xf0073200ul,
 161         .sdrfc          = 0x00001457ul,
 162 };
 163
 164 /************************* *****************************/
 165 static struct ddr3_phy_config ddr3phy_1333_64 = {
 166         .pllcr          = 0x0005C000ul,
 167         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
 168         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
 169         .ptr0           = 0x42C21590ul,
 170         .ptr1           = 0xD05612C0ul,
 171         .ptr2           = 0, /* not set in gel */
 172         .ptr3           = 0x0B4515C2ul,
 173         .ptr4           = 0x0A6E08B4ul,
 174         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
 175         .dcr_val        = ((1 << 10) | (1 << 27)),
 176         .dtpr0          = 0x8558AA55ul,
 177         .dtpr1          = 0x12857280ul,
 178         .dtpr2          = 0x5002C200ul,
 179         .mr0            = 0x00001A60ul,
 180         .mr1            = 0x00000006ul,
 181         .mr2            = 0x00000010ul,
 182         .dtcr           = 0x710035C7ul,
 183         .pgcr2          = 0x00F065B8ul,
 184         .zq0cr1         = 0x0000005Dul,
 185         .zq1cr1         = 0x0000005Bul,
 186         .zq2cr1         = 0x0000005Bul,
 187         .pir_v1         = 0x00000033ul,
 188         .pir_v2         = 0x0000FF81ul,
 189 };
 190 /******************************************************/
 191
 192 /* DDR PHY Configs Updated for PG 2.0
 193  * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */
 194 static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = {
 195         .pllcr          = 0x0001C000ul,
 196         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
 197         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
 198         .ptr0           = 0x42C21590ul,
 199         .ptr1           = 0xD05612C0ul,
 200         .ptr2           = 0, /* not set in gel */
 201         .ptr3           = 0x0D861A80ul,
 202         .ptr4           = 0x0C827100ul,
 203         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
 204         .dcr_val        = ((1 << 10)),
 205         .dtpr0          = 0xA19DBB66ul,
 206         .dtpr1          = 0x32868300ul,
 207         .dtpr2          = 0x50035200ul,
 208         .mr0            = 0x00001C70ul,
 209         .mr1            = 0x00000006ul,
 210         .mr2            = 0x00000018ul,
 211         .dtcr           = 0x730035C7ul,
 212         .pgcr2          = 0x00F07A12ul,
 213         .zq0cr1         = 0x0001005Dul,
 214         .zq1cr1         = 0x0001005Bul,
 215         .zq2cr1         = 0x0001005Bul,
 216         .pir_v1         = 0x00000033ul,
 217         .pir_v2         = 0x0000FF81ul,
 218 };
 219
 220 static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = {
 221         .pllcr          = 0x0005C000ul,
 222         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
 223         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
 224         .ptr0           = 0x42C21590ul,
 225         .ptr1           = 0xD05612C0ul,
 226         .ptr2           = 0, /* not set in gel */
 227         .ptr3           = 0x0B4515C2ul,
 228         .ptr4           = 0x0A6E08B4ul,
 229         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
 230         .dcr_val        = ((1 << 10)),
 231         .dtpr0          = 0x8558AA55ul,
 232         .dtpr1          = 0x32857280ul,
 233         .dtpr2          = 0x5002C200ul,
 234         .mr0            = 0x00001A60ul,
 235         .mr1            = 0x00000006ul,
 236         .mr2            = 0x00000010ul,
 237         .dtcr           = 0x710035C7ul,
 238         .pgcr2          = 0x00F065B8ul,
 239         .zq0cr1         = 0x0001005Dul,
 240         .zq1cr1         = 0x0001005Bul,
 241         .zq2cr1         = 0x0001005Bul,
 242         .pir_v1         = 0x00000033ul,
 243         .pir_v2         = 0x0000FF81ul,
 244 };
 245
 246 int get_dimm_params(char *dimm_name)
 247 {
 248         u8 spd_params[256];
 249         int ret;
 250         int old_bus;
 251
 252         i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
 253
 254         old_bus = i2c_get_bus_num();
 255         i2c_set_bus_num(1);
 256
 257         ret = i2c_read(0x53, 0, 1, spd_params, 256);
 258
 259         i2c_set_bus_num(old_bus);
 260
 261         dimm_name[0] = '\0';
 262
 263         if (ret) {
 264                 puts("Cannot read DIMM params\n");
 265                 return 1;
 266         }
 267
 268         /*
 269          * We need to convert spd data to dimm parameters
 270          * and to DDR3 EMIF and PHY regirsters values.
 271          * For now we just return DIMM type string value.
 272          * Caller may use this value to choose appropriate
 273          * a pre-set DDR3 configuration
 274          */
 275
 276         strncpy(dimm_name, (char *)&spd_params[0x80], 18);
 277         dimm_name[18] = '\0';
 278
 279         return 0;
 280 }
 281
 282 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
 283 struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
 284 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
 285 struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
 286
 287 void ddr3_init(void)
 288 {
 289         char dimm_name[32];
 290
 291         get_dimm_params(dimm_name);
 292
 293         printf("Detected SO-DIMM [%s]\n", dimm_name);
 294
 295         if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
 296                 init_pll(&ddr3a_400);
 297                 if (cpu_revision() > 0) {
 298                         if (cpu_revision() > 1) {
 299                                 /* PG 2.0 */
 300                                 /* Reset DDR3A PHY after PLL enabled */
 301                                 ddr3_reset_ddrphy();
 302                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
 303                                                  &ddr3phy_1600_64A_pg2);
 304                         } else {
 305                                 /* PG 1.1 */
 306                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
 307                                                  &ddr3phy_1600_64A);
 308                         }
 309
 310                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
 311                                           &ddr3_1600_64);
 312                         printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
 313                 } else {
 314                         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32);
 315                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
 316                                           &ddr3_1600_32);
 317                         printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
 318                 }
 319         } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
 320                 init_pll(&ddr3a_333);
 321                 if (cpu_revision() > 0) {
 322                         if (cpu_revision() > 1) {
 323                                 /* PG 2.0 */
 324                                 /* Reset DDR3A PHY after PLL enabled */
 325                                 ddr3_reset_ddrphy();
 326                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
 327                                                  &ddr3phy_1333_64A_pg2);
 328                         } else {
 329                                 /* PG 1.1 */
 330                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
 331                                                  &ddr3phy_1333_64A);
 332                         }
 333                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
 334                                           &ddr3_1333_64);
 335                 } else {
 336                         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32);
 337                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
 338                                           &ddr3_1333_32);
 339                 }
 340         } else {
 341                 printf("Unknown SO-DIMM. Cannot configure DDR3\n");
 342                 while (1)
 343                         ;
 344         }
 345
 346         init_pll(&ddr3b_333);
 347         ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64);
 348         ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
 349 }