3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
13 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #if defined(CONFIG_OMAP1610)
37 #include <./configs/omap1510.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 #ifdef CONFIG_CS_AUTOBOOT
43 unsigned long omap_flash_base;
46 void flash__init (void);
47 void ether__init (void);
48 void set_muxconf_regs (void);
49 void peripheral_power_enable (void);
51 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
53 static inline void delay (unsigned long loops)
55 __asm__ volatile ("1:\n"
57 "bne 1b":"=r" (loops):"0" (loops));
61 * Miscellaneous platform dependent initialisations
66 if (machine_is_omap_h2())
67 gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
68 else if (machine_is_omap_innovator())
69 gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
71 gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC;
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = 0x10000100;
76 /* Configure MUX settings */
78 peripheral_power_enable ();
80 /* this speeds up your boot a quite a bit. However to make it
81 * work, you need make sure your kernel startup flush bug is fixed.
92 int misc_init_r (void)
98 /******************************
101 ******************************/
102 void flash__init (void)
104 #define EMIFS_GlB_Config_REG 0xfffecc0c
107 #ifdef CONFIG_CS_AUTOBOOT
108 /* Check swapping of CS0 and CS3, set flash base accordingly */
109 omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
110 PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
112 regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
113 /* Turn off write protection for flash devices. */
114 regval = regval | 0x0001;
115 *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
117 /*************************************************************
119 Description: take the Ethernet controller out of reset and wait
120 for the EEPROM load to complete.
121 *************************************************************/
122 void ether__init (void)
124 #define ETH_CONTROL_REG 0x0400030b
126 #ifdef CONFIG_H2_OMAP1610
127 #define LAN_RESET_REGISTER 0x0400001c
129 /* The debug board on which the lan chip resides may not be powered
130 * ON at the same time as the OMAP chip. So wait in a loop until the
131 * lan reset register (on the debug board) is available (powered on)
132 * and reset the lan chip.
135 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
137 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
139 } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
142 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
144 } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
147 *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
151 /******************************
154 ******************************/
157 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
158 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
163 /******************************************************
164 Routine: set_muxconf_regs
165 Description: Setting up the configuration Mux registers
166 specific to the hardware
167 *******************************************************/
168 void set_muxconf_regs (void)
170 volatile unsigned int *MuxConfReg;
171 /* set each registers to its reset value; */
173 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
174 /* setup for UART1 */
175 *MuxConfReg &= ~(0x02000000); /* bit 25 */
176 /* setup for UART2 */
177 *MuxConfReg &= ~(0x01000000); /* bit 24 */
178 /* Disable Uwire CS Hi-Z */
179 *MuxConfReg |= 0x08000000;
181 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
182 *MuxConfReg = 0x00000000;
184 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
185 *MuxConfReg = 0x00000000;
187 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
188 *MuxConfReg = 0x00000000;
190 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
191 /*setup mux for UART3 */
192 *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
193 *MuxConfReg &= ~0x0000003e;
195 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
196 *MuxConfReg = 0x00000000;
198 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
199 /* Disable Uwire CS Hi-Z */
200 *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
202 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
203 /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
204 /* hardware will actually use TX and RTS based on bit 25 in */
205 /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
206 *MuxConfReg |= 0x00201000;
208 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
209 *MuxConfReg = 0x00000000;
211 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
212 *MuxConfReg = 0x00000000;
214 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
215 /* setup for UART2 */
216 /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
217 /* hardware will actually use TX and RTS based on bit 24 in */
218 /* FUNC_MUX_CTRL_0. */
219 *MuxConfReg |= 0x09000000;
221 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
222 *MuxConfReg = 0x00000000;
224 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
225 *MuxConfReg = 0x00000000;
226 /* mux setup for SD/MMC driver */
228 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
229 *MuxConfReg &= 0xFFFE0FFF;
231 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
232 *MuxConfReg = 0x00000000;
234 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
235 /* bit 13 for MMC2 XOR_CLK */
236 *MuxConfReg &= ~(0x00002000);
237 /* bit 29 for UART 1 */
238 *MuxConfReg &= ~(0x00002000);
240 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
241 /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
242 *MuxConfReg |= 0x000C0000;
244 (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
245 *MuxConfReg &= ~(0x00000070);
246 *MuxConfReg &= ~(0x00000008);
247 *MuxConfReg |= 0x00000003;
248 *MuxConfReg |= 0x00000180;
250 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
251 /* bit 17, software controls VBUS */
252 *MuxConfReg &= ~(0x00020000);
253 /* Enable USB 48 and 12M clocks */
254 *MuxConfReg |= 0x00000200;
255 *MuxConfReg &= ~(0x00000180);
256 /*2.75V for MMCSDIO1 */
258 (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
259 *MuxConfReg = 0x00001FE7;
261 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
262 *MuxConfReg = 0x00000000;
264 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
265 *MuxConfReg = 0x00000000;
267 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
268 *MuxConfReg = 0x00000000;
270 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
271 *MuxConfReg = 0x00000000;
273 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
274 *MuxConfReg = 0x00000000;
276 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
277 *MuxConfReg = 0x00000000;
278 /* Turn on UART2 48 MHZ clock */
280 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
281 *MuxConfReg |= 0x40000000;
283 (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
284 /* setup for USB VBus detection OMAP161x */
285 *MuxConfReg |= 0x00040000; /* bit 18 */
287 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
288 /* PullUps for SD/MMC driver */
289 *MuxConfReg |= ~(0xFFFE0FFF);
291 (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
292 *MuxConfReg = COMP_MODE_ENABLE;
295 /******************************************************
296 Routine: peripheral_power_enable
297 Description: Enable the power for UART1
298 *******************************************************/
299 void peripheral_power_enable (void)
301 #define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
302 #define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
304 *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
307 #ifdef CONFIG_CMD_NET
308 int board_eth_init(bd_t *bis)
311 #ifdef CONFIG_LAN91C96
312 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);