3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/omap2420.h>
28 #include <asm/arch/bits.h>
29 #include <asm/arch/mux.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/sys_info.h>
32 #include <asm/arch/mem.h>
34 #include <asm/mach-types.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 void wait_for_command_complete(unsigned int wd_base);
40 /*******************************************************
42 * Description: spinning delay to use before udelay works
43 ******************************************************/
44 static inline void delay (unsigned long loops)
46 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
47 "bne 1b":"=r" (loops):"0" (loops));
50 /*****************************************
52 * Description: Early hardware init.
53 *****************************************/
56 gpmc_init(); /* in SRAM or SDRM, finish GPMC */
58 gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
59 gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */
64 /**********************************************************
65 * Routine: try_unlock_sram()
66 * Description: If chip is GP type, unlock the SRAM for
68 ***********************************************************/
69 void try_unlock_sram(void)
71 /* if GP device unlock device SRAM for general use */
72 if (get_device_type() == GP_DEVICE) {
73 __raw_writel(0xFF, A_REQINFOPERM0);
74 __raw_writel(0xCFDE, A_READPERM0);
75 __raw_writel(0xCFDE, A_WRITEPERM0);
79 /**********************************************************
81 * Description: Does early system init of muxing and clocks.
82 * - Called path is with sram stack.
83 **********************************************************/
86 int in_sdram = running_in_sdram();
102 /*******************************************************
103 * Routine: misc_init_r
104 * Description: Init ethernet (done here so udelay works)
105 ********************************************************/
106 int misc_init_r (void)
108 ether_init(); /* better done here so timers are init'ed */
112 /****************************************
113 * Routine: watchdog_init
114 * Description: Shut down watch dogs
115 *****************************************/
116 void watchdog_init(void)
118 /* There are 4 watch dogs. 1 secure, and 3 general purpose.
119 * The ROM takes care of the secure one. Of the 3 GP ones,
120 * 1 can reset us directly, the other 2 only generate MPU interrupts.
122 __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
123 wait_for_command_complete(WD2_BASE);
124 __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
126 #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
127 __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
128 wait_for_command_complete(WD3_BASE);
129 __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
131 __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
132 wait_for_command_complete(WD4_BASE);
133 __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
137 /******************************************************
138 * Routine: wait_for_command_complete
139 * Description: Wait for posting to finish on watchdog
140 ******************************************************/
141 void wait_for_command_complete(unsigned int wd_base)
145 pending = __raw_readl(wd_base+WWPS);
149 /*******************************************************************
151 * Description: take the Ethernet controller out of reset and wait
152 * for the EEPROM load to complete.
153 ******************************************************************/
154 void ether_init (void)
156 #ifdef CONFIG_LAN91C96
159 __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
161 __raw_writew(0x0, LAN_RESET_REGISTER);
163 __raw_writew(0x1, LAN_RESET_REGISTER);
166 goto h4reset_err_out;
168 } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
173 __raw_writew(0x0, LAN_RESET_REGISTER);
176 goto h4reset_err_out;
178 } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
181 *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
189 /**********************************************
191 * Description: sets uboots idea of sdram size
192 **********************************************/
195 unsigned int size0=0,size1=0;
197 u8 chg_on = 0x5; /* enable charge of back up battery */
201 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
203 btype = get_board_type();
204 mtype = get_mem_type();
206 display_board_info(btype);
207 if (btype == BOARD_H4_MENELAUS){
208 update_mux(btype,mtype); /* combo part on menelaus */
209 i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
210 i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
213 if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
214 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
216 size0 = get_sdr_cs_size(SDRC_CS0_OSET);
217 size1 = get_sdr_cs_size(SDRC_CS1_OSET);
219 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1);
224 void dram_init_banksize(void)
226 unsigned int size0, size1;
230 size0 = get_sdr_cs_size(SDRC_CS0_OSET);
231 size1 = get_sdr_cs_size(SDRC_CS1_OSET);
233 if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
234 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
235 else /* ES2 and above can remap at 32MB granularity */
236 gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
237 gd->bd->bi_dram[1].size = size1;
239 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
240 gd->bd->bi_dram[0].size = size0;
243 /**********************************************************
244 * Routine: set_muxconf_regs
245 * Description: Setting up the configuration Mux registers
246 * specific to the hardware
247 *********************************************************/
248 void set_muxconf_regs (void)
259 muxSetupTouchScreen();
263 /*****************************************************************
264 * Routine: peripheral_enable
265 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
266 ******************************************************************/
267 void peripheral_enable(void)
269 unsigned int v, if_clks=0, func_clks=0;
271 /* Enable GP2 timer.*/
274 v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
275 __raw_writel(v, CM_CLKSEL2_CORE);
276 __raw_writel(0x1, CM_CLKSEL_WKUP);
278 #ifdef CONFIG_SYS_NS16550
279 /* Enable UART1 clock */
283 v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
284 __raw_writel(v,CM_ICLKEN1_CORE );
285 v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
286 __raw_writel(v, CM_FCLKEN1_CORE);
289 #ifndef KERNEL_UPDATED
291 #define V1 0xffffffff
292 #define V2 0x00000007
294 __raw_writel(V1, CM_FCLKEN1_CORE);
295 __raw_writel(V2, CM_FCLKEN2_CORE);
296 __raw_writel(V1, CM_ICLKEN1_CORE);
297 __raw_writel(V1, CM_ICLKEN2_CORE);
302 /****************************************
303 * Routine: muxSetupUsb0 (ostboot)
304 * Description: Setup usb muxing
305 *****************************************/
306 void muxSetupUsb0(void)
308 volatile uint8 *MuxConfigReg;
309 volatile uint32 *otgCtrlReg;
311 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
312 *MuxConfigReg &= (uint8)(~0x1F);
314 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
315 *MuxConfigReg &= (uint8)(~0x1F);
317 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
318 *MuxConfigReg &= (uint8)(~0x1F);
320 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
321 *MuxConfigReg &= (uint8)(~0x1F);
323 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
324 *MuxConfigReg &= (uint8)(~0x1F);
326 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
327 *MuxConfigReg &= (uint8)(~0x1F);
329 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
330 *MuxConfigReg &= (uint8)(~0x1F);
332 /* setup for USB VBus detection */
333 otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
334 *otgCtrlReg |= 0x00040000; /* bit 18 */
337 /****************************************
338 * Routine: muxSetupUart3 (ostboot)
339 * Description: Setup uart3 muxing
340 *****************************************/
341 void muxSetupUart3(void)
343 volatile uint8 *MuxConfigReg;
345 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
346 *MuxConfigReg &= (uint8)(~0x1F);
348 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
349 *MuxConfigReg &= (uint8)(~0x1F);
352 /****************************************
353 * Routine: muxSetupI2C1 (ostboot)
354 * Description: Setup i2c muxing
355 *****************************************/
356 void muxSetupI2C1(void)
358 volatile unsigned char *MuxConfigReg;
360 /* I2C1 Clock pin configuration, PIN = M19 */
361 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
362 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
364 /* I2C1 Data pin configuration, PIN = L15 */
365 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
366 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
368 /* Pull-up required on data line */
369 /* external pull-up already present. */
370 /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
373 /****************************************
374 * Routine: muxSetupUART1 (ostboot)
375 * Description: Set up uart1 muxing
376 *****************************************/
377 void muxSetupUART1(void)
379 volatile unsigned char *MuxConfigReg;
381 /* UART1_CTS pin configuration, PIN = D21 */
382 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
383 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
385 /* UART1_RTS pin configuration, PIN = H21 */
386 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
387 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
389 /* UART1_TX pin configuration, PIN = L20 */
390 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
391 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
393 /* UART1_RX pin configuration, PIN = T21 */
394 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
395 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
398 /****************************************
399 * Routine: muxSetupLCD (ostboot)
400 * Description: Setup lcd muxing
401 *****************************************/
402 void muxSetupLCD(void)
404 volatile unsigned char *MuxConfigReg;
406 /* LCD_D0 pin configuration, PIN = Y7 */
407 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
408 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
410 /* LCD_D1 pin configuration, PIN = P10 */
411 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
412 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
414 /* LCD_D2 pin configuration, PIN = V8 */
415 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
416 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
418 /* LCD_D3 pin configuration, PIN = Y8 */
419 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
420 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
422 /* LCD_D4 pin configuration, PIN = W8 */
423 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
424 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
426 /* LCD_D5 pin configuration, PIN = R10 */
427 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
428 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
430 /* LCD_D6 pin configuration, PIN = Y9 */
431 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
432 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
434 /* LCD_D7 pin configuration, PIN = V9 */
435 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
436 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
438 /* LCD_D8 pin configuration, PIN = W9 */
439 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
440 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
442 /* LCD_D9 pin configuration, PIN = P11 */
443 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
444 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
446 /* LCD_D10 pin configuration, PIN = V10 */
447 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
448 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
450 /* LCD_D11 pin configuration, PIN = Y10 */
451 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
452 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
454 /* LCD_D12 pin configuration, PIN = W10 */
455 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
456 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
458 /* LCD_D13 pin configuration, PIN = R11 */
459 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
460 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
462 /* LCD_D14 pin configuration, PIN = V11 */
463 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
464 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
466 /* LCD_D15 pin configuration, PIN = W11 */
467 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
468 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
470 /* LCD_D16 pin configuration, PIN = P12 */
471 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
472 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
474 /* LCD_D17 pin configuration, PIN = R12 */
475 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
476 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
478 /* LCD_PCLK pin configuration, PIN = W6 */
479 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
480 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
482 /* LCD_VSYNC pin configuration, PIN = V7 */
483 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
484 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
486 /* LCD_HSYNC pin configuration, PIN = Y6 */
487 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
488 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
490 /* LCD_ACBIAS pin configuration, PIN = W7 */
491 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
492 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
495 /****************************************
496 * Routine: muxSetupCamera (ostboot)
497 * Description: Setup camera muxing
498 *****************************************/
499 void muxSetupCamera(void)
501 volatile unsigned char *MuxConfigReg;
503 /* CAMERA_RSTZ pin configuration, PIN = Y16 */
504 /* CAM_RST is connected through the I2C IO expander.*/
505 /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
506 /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */
508 /* CAMERA_XCLK pin configuration, PIN = U3 */
509 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
510 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
512 /* CAMERA_LCLK pin configuration, PIN = V5 */
513 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
514 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
516 /* CAMERA_VSYNC pin configuration, PIN = U2 */
517 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
518 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
520 /* CAMERA_HSYNC pin configuration, PIN = T3 */
521 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
522 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
524 /* CAMERA_DAT0 pin configuration, PIN = T4 */
525 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
526 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
528 /* CAMERA_DAT1 pin configuration, PIN = V2 */
529 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
530 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
532 /* CAMERA_DAT2 pin configuration, PIN = V3 */
533 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
534 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
536 /* CAMERA_DAT3 pin configuration, PIN = U4 */
537 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
538 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
540 /* CAMERA_DAT4 pin configuration, PIN = W2 */
541 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
542 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
544 /* CAMERA_DAT5 pin configuration, PIN = V4 */
545 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
546 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
548 /* CAMERA_DAT6 pin configuration, PIN = W3 */
549 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
550 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
552 /* CAMERA_DAT7 pin configuration, PIN = Y2 */
553 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
554 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
556 /* CAMERA_DAT8 pin configuration, PIN = Y4 */
557 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
558 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
560 /* CAMERA_DAT9 pin configuration, PIN = V6 */
561 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
562 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
565 /****************************************
566 * Routine: muxSetupMMCSD (ostboot)
567 * Description: set up MMC muxing
568 *****************************************/
569 void muxSetupMMCSD(void)
571 volatile unsigned char *MuxConfigReg;
573 /* SDMMC_CLKI pin configuration, PIN = H15 */
574 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
575 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
577 /* SDMMC_CLKO pin configuration, PIN = G19 */
578 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
579 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
581 /* SDMMC_CMD pin configuration, PIN = H18 */
582 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
583 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
584 /* External pull-ups are present. */
585 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
587 /* SDMMC_DAT0 pin configuration, PIN = F20 */
588 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
589 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
590 /* External pull-ups are present. */
591 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
593 /* SDMMC_DAT1 pin configuration, PIN = H14 */
594 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
595 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
596 /* External pull-ups are present. */
597 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
599 /* SDMMC_DAT2 pin configuration, PIN = E19 */
600 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
601 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
602 /* External pull-ups are present. */
603 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
605 /* SDMMC_DAT3 pin configuration, PIN = D19 */
606 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
607 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
608 /* External pull-ups are present. */
609 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
611 /* SDMMC_DDIR0 pin configuration, PIN = F19 */
612 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
613 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
615 /* SDMMC_DDIR1 pin configuration, PIN = E20 */
616 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
617 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
619 /* SDMMC_DDIR2 pin configuration, PIN = F18 */
620 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
621 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
623 /* SDMMC_DDIR3 pin configuration, PIN = E18 */
624 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
625 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
627 /* SDMMC_CDIR pin configuration, PIN = G18 */
628 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
629 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
631 /* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/
632 /* MMC_CD for 2422IP=K1 */
633 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
634 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
636 /* MMC_WP pin configuration, PIN = B4 */
637 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
638 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
641 /******************************************
642 * Routine: muxSetupTouchScreen (ostboot)
643 * Description: Set up touch screen muxing
644 *******************************************/
645 void muxSetupTouchScreen(void)
647 volatile unsigned char *MuxConfigReg;
649 /* SPI1_CLK pin configuration, PIN = U18 */
650 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
651 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
653 /* SPI1_MOSI pin configuration, PIN = V20 */
654 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
655 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
657 /* SPI1_MISO pin configuration, PIN = T18 */
658 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
659 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
661 /* SPI1_nCS0 pin configuration, PIN = U19 */
662 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
663 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
665 /* PEN_IRQ pin configuration, PIN = P20 */
666 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
667 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
670 /****************************************
671 * Routine: muxSetupHDQ (ostboot)
672 * Description: setup 1wire mux
673 *****************************************/
674 void muxSetupHDQ(void)
676 volatile unsigned char *MuxConfigReg;
678 /* HDQ_SIO pin configuration, PIN = N18 */
679 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
680 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
683 /***************************************************************
684 * Routine: muxSetupGPMC (ostboot)
685 * Description: Configures balls which cam up in protected mode
686 ***************************************************************/
687 void muxSetupGPMC(void)
689 volatile uint8 *MuxConfigReg;
690 volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
696 /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */
697 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
698 *MuxConfigReg = 0x00 ;
700 /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */
701 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
702 *MuxConfigReg = 0x01 ;
704 /* MPDB(Multi Port Debug Port) CS1 */
705 /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
706 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
707 *MuxConfigReg = 0x00 ;
709 /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
710 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
711 *MuxConfigReg = 0x00 ;
714 /****************************************************************
715 * Routine: muxSetupSDRC (ostboot)
716 * Description: Configures balls which come up in protected mode
717 ****************************************************************/
718 void muxSetupSDRC(void)
720 volatile uint8 *MuxConfigReg;
722 /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */
723 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
724 *MuxConfigReg = 0x00 ;
726 /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */
727 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
728 *MuxConfigReg = 0x00 ;
730 /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */
731 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
732 *MuxConfigReg = 0x00;
734 if (get_cpu_type() == CPU_2422) {
735 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
736 *MuxConfigReg = 0x1b;
740 /*****************************************************************************
741 * Routine: update_mux()
742 * Description: Update balls which are different beween boards. All should be
743 * updated to match functionaly. However, I'm only updating ones
744 * which I'll be using for now. When power comes into play they
746 *****************************************************************************/
747 void update_mux(u32 btype,u32 mtype)
749 u32 cpu, base = OMAP2420_CTRL_BASE;
750 cpu = get_cpu_type();
752 if (btype == BOARD_H4_MENELAUS) {
753 if (cpu == CPU_2420) {
754 /* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/
755 __raw_writeb(0x3, base+0x30);
756 /* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/
757 __raw_writeb(0x3, base+0xa3);
758 /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
759 /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
760 /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
761 /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
762 /* PIN = M1 (HSUSBOTG) */
763 /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
764 __raw_writeb(0x3, base+0x9d);
765 /* PIN = U32, (WLAN_CLKREQ) */
766 /* PIN = Y11, WLAN */
767 /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
768 __raw_writeb(0x3, base+0xe7);
769 /* PIN = AA8, mDOC */
771 /* PIN = AA13, WLAN */
772 /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
773 __raw_writeb(0x3, base+0x10e);
774 /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
775 __raw_writeb(0x3, base+0x110);
776 /* PIN = J15 HHUSB */
777 /* PIN = H19 HSUSB */
778 /* PIN = W13, P13, R13, W16 ... */
779 /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
780 __raw_writeb(0x3, base+0xde);
781 /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
782 __raw_writeb(0x0, base+0x12c);
783 /* PIN = AA17->sys_clkreq mode 0 -DO- */
784 __raw_writeb(0x0, base+0x136);
785 } else if (cpu == CPU_2422) {
786 /* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/
787 /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
788 /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
789 /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
790 /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
791 __raw_writeb(0x0, base+0x92);
792 /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
793 /* PIN = M1 (HSUSBOTG) */
794 /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
795 __raw_writeb(0x3, base+0x10c);
796 /* PIN = U32, (WLAN_CLKREQ) */
797 /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
798 __raw_writeb(0x3, base+0x30);
799 /* PIN = AA8, mDOC */
801 /* PIN = AA12, WLAN */
802 /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
803 __raw_writeb(0x3, base+0x10e);
804 /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
805 __raw_writeb(0x3, base+0x110);
806 /* PIN = J15 HHUSB */
807 /* PIN = H19 HSUSB */
808 /* PIN = W13, P13, R13, W16 ... */
809 /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
810 __raw_writeb(0x3, base+0xde);
811 /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
812 __raw_writeb(0x0, base+0x12c);
813 /* PIN = AA17->sys_clkreq mode 0 -DO- */
814 __raw_writeb(0x0, base+0x136);
817 } else if (btype == BOARD_H4_SDP) {
818 if (cpu == CPU_2420) {
819 /* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/
820 /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
825 /* Pin = AA10 VLNQ */
826 /* Pin = AA12 VLNQ */
827 /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
828 __raw_writeb(0x3, base+0x10e);
829 /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
830 __raw_writeb(0x3, base+0x110);
831 /* PIN = J15 MDOC_nDMAREQ */
832 /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
833 __raw_writeb(0x3, base+0x114);
834 /* PIN = W13, V12, P13, R13, W19, W16 ... */
835 /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
836 } else if (cpu == CPU_2422) {
837 /* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */
838 /* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/
843 /* Pin = AA10 VLNQ */
844 /* Pin = AA12 VLNQ */
845 /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
846 __raw_writeb(0x3, base+0x10e);
847 /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
848 __raw_writeb(0x3, base+0x110);
849 /* PIN = J15 MDOC_nDMAREQ */
850 /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
851 __raw_writeb(0x3, base+0x114);
852 /* PIN = W13, V12, P13, R13, W19, W16 ... */
853 /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
858 #ifdef CONFIG_CMD_NET
859 int board_eth_init(bd_t *bis)
862 #ifdef CONFIG_LAN91C96
863 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);