2 * (C) Copyright 2004-2009
3 * Texas Instruments Incorporated, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/mux.h>
29 #include <asm/arch/mem.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/mach-types.h>
34 const omap3_sysinfo sysinfo = {
36 "OMAP3 SDP3430 board",
37 #if defined(CONFIG_ENV_IS_IN_ONENAND)
39 #elif defined(CONFIG_ENV_IS_IN_NAND)
46 /* Timing definitions for GPMC controller for Sibley NOR */
47 static const u32 gpmc_sdp_nor[] = {
48 SDP3430_NOR_GPMC_CONF1,
49 SDP3430_NOR_GPMC_CONF2,
50 SDP3430_NOR_GPMC_CONF3,
51 SDP3430_NOR_GPMC_CONF4,
52 SDP3430_NOR_GPMC_CONF5,
53 SDP3430_NOR_GPMC_CONF6,
54 /*CONF7- computed as params */
58 * Timing definitions for GPMC controller for Debug Board
59 * Debug board contains access to ethernet and DIP Switch setting
62 static const u32 gpmc_sdp_debug[] = {
63 SDP3430_DEBUG_GPMC_CONF1,
64 SDP3430_DEBUG_GPMC_CONF2,
65 SDP3430_DEBUG_GPMC_CONF3,
66 SDP3430_DEBUG_GPMC_CONF4,
67 SDP3430_DEBUG_GPMC_CONF5,
68 SDP3430_DEBUG_GPMC_CONF6,
69 /*CONF7- computed as params */
72 /* Timing defintions for GPMC OneNAND */
73 static const u32 gpmc_sdp_onenand[] = {
74 SDP3430_ONENAND_GPMC_CONF1,
75 SDP3430_ONENAND_GPMC_CONF2,
76 SDP3430_ONENAND_GPMC_CONF3,
77 SDP3430_ONENAND_GPMC_CONF4,
78 SDP3430_ONENAND_GPMC_CONF5,
79 SDP3430_ONENAND_GPMC_CONF6,
80 /*CONF7- computed as params */
83 /* GPMC definitions for GPMC NAND */
84 static const u32 gpmc_sdp_nand[] = {
85 SDP3430_NAND_GPMC_CONF1,
86 SDP3430_NAND_GPMC_CONF2,
87 SDP3430_NAND_GPMC_CONF3,
88 SDP3430_NAND_GPMC_CONF4,
89 SDP3430_NAND_GPMC_CONF5,
90 SDP3430_NAND_GPMC_CONF6,
91 /*CONF7- computed as params */
94 /* gpmc_cfg is initialized by gpmc_init and we use it here */
95 extern struct gpmc *gpmc_cfg;
98 * @brief board_init - gpmc and basic setup as phase1 of boot sequence
104 DECLARE_GLOBAL_DATA_PTR;
106 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
107 /* TODO: Dynamically pop out CS mapping and program accordingly */
108 /* Configure devices for default ON ON ON settings */
109 enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
110 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
111 enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
113 enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
115 enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
117 /* board id for Linux */
118 gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
119 /* boot param addr */
120 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
125 #define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
126 #define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
129 * @brief board_eth_init Take the Ethernet controller out of reset and wait
130 * for the EEPROM load to complete.
132 int board_eth_init(bd_t *bis)
135 #ifdef CONFIG_LAN91C96
138 writew(0x0, LAN_RESET_REGISTER);
140 writew(0x1, LAN_RESET_REGISTER);
145 } while (readw(LAN_RESET_REGISTER) != 0x1);
150 writew(0x0, LAN_RESET_REGISTER);
155 } while (readw(LAN_RESET_REGISTER) != 0x0000);
158 writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
160 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
168 * @brief misc_init_r - Configure SDP board specific configurations
169 * such as power configurations, ethernet initialization as phase2 of
174 int misc_init_r(void)
177 * VAUX3 - 2.8V for DVI
180 * and turns on LEDA/LEDB (not needed ... NOP?)
182 twl4030_power_init();
184 /* FIXME finish setup:
185 * VAUX1 - 2.8V for mainboard I/O
186 * VAUX2 - 2.8V for camera
187 * VAUX4 - 1.8V for OMAP3 CSI
188 * VMMC1 - 3.15V (init, variable) for MMC1
189 * VMMC2 - 1.85V for MMC2
190 * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
198 * @brief set_muxconf_regs Setting up the configuration Mux registers
199 * specific to the hardware. Many pins need to be moved from protect
202 void set_muxconf_regs(void)
204 /* platform specific muxes */