2 * (C) Copyright 2004-2009
3 * Texas Instruments Incorporated, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/mmc_host_def.h>
13 #include <asm/arch/mux.h>
14 #include <asm/arch/mem.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-types.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 const omap3_sysinfo sysinfo = {
23 "OMAP3 SDP3430 board",
24 #if defined(CONFIG_ENV_IS_IN_ONENAND)
26 #elif defined(CONFIG_ENV_IS_IN_NAND)
33 /* Timing definitions for GPMC controller for Sibley NOR */
34 static const u32 gpmc_sdp_nor[] = {
35 SDP3430_NOR_GPMC_CONF1,
36 SDP3430_NOR_GPMC_CONF2,
37 SDP3430_NOR_GPMC_CONF3,
38 SDP3430_NOR_GPMC_CONF4,
39 SDP3430_NOR_GPMC_CONF5,
40 SDP3430_NOR_GPMC_CONF6,
41 /*CONF7- computed as params */
45 * Timing definitions for GPMC controller for Debug Board
46 * Debug board contains access to ethernet and DIP Switch setting
49 static const u32 gpmc_sdp_debug[] = {
50 SDP3430_DEBUG_GPMC_CONF1,
51 SDP3430_DEBUG_GPMC_CONF2,
52 SDP3430_DEBUG_GPMC_CONF3,
53 SDP3430_DEBUG_GPMC_CONF4,
54 SDP3430_DEBUG_GPMC_CONF5,
55 SDP3430_DEBUG_GPMC_CONF6,
56 /*CONF7- computed as params */
59 /* Timing defintions for GPMC OneNAND */
60 static const u32 gpmc_sdp_onenand[] = {
61 SDP3430_ONENAND_GPMC_CONF1,
62 SDP3430_ONENAND_GPMC_CONF2,
63 SDP3430_ONENAND_GPMC_CONF3,
64 SDP3430_ONENAND_GPMC_CONF4,
65 SDP3430_ONENAND_GPMC_CONF5,
66 SDP3430_ONENAND_GPMC_CONF6,
67 /*CONF7- computed as params */
70 /* GPMC definitions for GPMC NAND */
71 static const u32 gpmc_sdp_nand[] = {
72 SDP3430_NAND_GPMC_CONF1,
73 SDP3430_NAND_GPMC_CONF2,
74 SDP3430_NAND_GPMC_CONF3,
75 SDP3430_NAND_GPMC_CONF4,
76 SDP3430_NAND_GPMC_CONF5,
77 SDP3430_NAND_GPMC_CONF6,
78 /*CONF7- computed as params */
81 /* gpmc_cfg is initialized by gpmc_init and we use it here */
82 extern struct gpmc *gpmc_cfg;
85 * @brief board_init - gpmc and basic setup as phase1 of boot sequence
91 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
92 /* TODO: Dynamically pop out CS mapping and program accordingly */
93 /* Configure devices for default ON ON ON settings */
94 enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
95 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
96 enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
98 enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
100 enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
102 /* board id for Linux */
103 gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
104 /* boot param addr */
105 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
110 #define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
111 #define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
114 * @brief board_eth_init Take the Ethernet controller out of reset and wait
115 * for the EEPROM load to complete.
117 int board_eth_init(bd_t *bis)
120 #ifdef CONFIG_LAN91C96
123 writew(0x0, LAN_RESET_REGISTER);
125 writew(0x1, LAN_RESET_REGISTER);
130 } while (readw(LAN_RESET_REGISTER) != 0x1);
135 writew(0x0, LAN_RESET_REGISTER);
140 } while (readw(LAN_RESET_REGISTER) != 0x0000);
143 writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
145 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
153 * @brief misc_init_r - Configure SDP board specific configurations
154 * such as power configurations, ethernet initialization as phase2 of
159 int misc_init_r(void)
162 * VAUX3 - 2.8V for DVI
165 * and turns on LEDA/LEDB (not needed ... NOP?)
167 twl4030_power_init();
169 /* FIXME finish setup:
170 * VAUX1 - 2.8V for mainboard I/O
171 * VAUX2 - 2.8V for camera
172 * VAUX4 - 1.8V for OMAP3 CSI
173 * VMMC1 - 3.15V (init, variable) for MMC1
174 * VMMC2 - 1.85V for MMC2
175 * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
183 * @brief set_muxconf_regs Setting up the configuration Mux registers
184 * specific to the hardware. Many pins need to be moved from protect
187 void set_muxconf_regs(void)
189 /* platform specific muxes */
193 #ifdef CONFIG_GENERIC_MMC
194 int board_mmc_init(bd_t *bis)
196 return omap_mmc_init(0, 0, 0, -1, -1);