4 * Board functions for TI814x EVM
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #ifdef CONFIG_SPL_BUILD
38 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
39 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
43 #ifdef CONFIG_SPL_BUILD
44 #define UART_RESET (0x1 << 1)
45 #define UART_CLK_RUNNING_MASK 0x1
46 #define UART_SMART_IDLE_EN (0x1 << 0x3)
48 static void rtc32k_enable(void)
50 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
53 * Unlock the RTC's registers. For more details please see the
54 * RTC_SS section of the TRM. In order to unlock we need to
55 * write these specific values (keys) in this order.
57 writel(0x83e70b13, &rtc->kick0r);
58 writel(0x95a4f1e0, &rtc->kick1r);
60 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
61 writel((1 << 3) | (1 << 6), &rtc->osc);
64 static void uart_enable(void)
69 regVal = readl(&uart_base->uartsyscfg);
71 writel(regVal, &uart_base->uartsyscfg);
72 while ((readl(&uart_base->uartsyssts) &
73 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
76 /* Disable smart idle */
77 regVal = readl(&uart_base->uartsyscfg);
78 regVal |= UART_SMART_IDLE_EN;
79 writel(regVal, &uart_base->uartsyscfg);
82 static void wdt_disable(void)
84 writel(0xAAAA, &wdtimer->wdtwspr);
85 while (readl(&wdtimer->wdtwwps) != 0x0)
87 writel(0x5555, &wdtimer->wdtwspr);
88 while (readl(&wdtimer->wdtwwps) != 0x0)
92 static const struct cmd_control evm_ddr2_cctrl_data = {
106 static const struct emif_regs evm_ddr2_emif0_regs = {
107 .sdram_config = 0x40801ab2,
108 .ref_ctrl = 0x10000c30,
109 .sdram_tim1 = 0x0aaaf552,
110 .sdram_tim2 = 0x043631d2,
111 .sdram_tim3 = 0x00000327,
112 .emif_ddr_phy_ctlr_1 = 0x00000007
115 static const struct emif_regs evm_ddr2_emif1_regs = {
116 .sdram_config = 0x40801ab2,
117 .ref_ctrl = 0x10000c30,
118 .sdram_tim1 = 0x0aaaf552,
119 .sdram_tim2 = 0x043631d2,
120 .sdram_tim3 = 0x00000327,
121 .emif_ddr_phy_ctlr_1 = 0x00000007
124 const struct dmm_lisa_map_regs evm_lisa_map_regs = {
125 .dmm_lisa_map_0 = 0x00000000,
126 .dmm_lisa_map_1 = 0x00000000,
127 .dmm_lisa_map_2 = 0x806c0300,
128 .dmm_lisa_map_3 = 0x806c0300,
131 static const struct ddr_data evm_ddr2_data = {
132 .datardsratio0 = ((0x35<<10) | (0x35<<0)),
133 .datawdsratio0 = ((0x20<<10) | (0x20<<0)),
134 .datawiratio0 = ((0<<10) | (0<<0)),
135 .datagiratio0 = ((0<<10) | (0<<0)),
136 .datafwsratio0 = ((0x90<<10) | (0x90<<0)),
137 .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
138 .datauserank0delay = 1,
144 * early system init of muxing and clocks.
148 #ifdef CONFIG_SPL_BUILD
149 /* WDT1 is already running when the bootloader gets control
150 * Disable it to avoid "random" resets
154 /* Setup the PLLs and the clocks for the peripherals */
157 /* Enable RTC32K clock */
161 enable_uart0_pin_mux();
164 enable_mmc1_pin_mux();
171 preloader_console_init();
173 config_dmm(&evm_lisa_map_regs);
175 config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
176 &evm_ddr2_emif0_regs, 0);
177 config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
178 &evm_ddr2_emif1_regs, 1);
183 * Basic board specific setup. Pinmux has been handled already.
187 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
191 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
192 int board_mmc_init(bd_t *bis)
194 omap_mmc_init(1, 0, 0, -1, -1);