1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2018 Toradex, Inc.
8 #include <asm/arch-tegra/ap.h>
11 #include <asm/arch/gpio.h>
12 #include <asm/arch/pinmux.h>
13 #include <pci_tegra.h>
14 #include <power/as3722.h>
15 #include <power/pmic.h>
17 #include "../common/tdx-common.h"
18 #include "pinmux-config-apalis-tk1.h"
20 #define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
21 #define LAN_RESET_N TEGRA_GPIO(S, 2)
22 #define LAN_WAKE_N TEGRA_GPIO(O, 5)
23 #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
24 #define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
25 #define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
26 #endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
28 int arch_misc_init(void)
30 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
32 printf("USB recovery mode\n");
39 puts("Model: Toradex Apalis TK1 2GB\n");
44 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
45 int ft_board_setup(void *blob, bd_t *bd)
47 return ft_common_board_setup(blob, bd);
52 * Routine: pinmux_init
53 * Description: Do individual peripheral pinmux configs
55 void pinmux_init(void)
57 pinmux_clear_tristate_input_clamping();
59 gpio_config_table(apalis_tk1_gpio_inits,
60 ARRAY_SIZE(apalis_tk1_gpio_inits));
62 pinmux_config_pingrp_table(apalis_tk1_pingrps,
63 ARRAY_SIZE(apalis_tk1_pingrps));
65 pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
66 ARRAY_SIZE(apalis_tk1_drvgrps));
69 #ifdef CONFIG_PCI_TEGRA
70 /* TODO: Convert to driver model */
71 static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
78 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
80 pr_err("failed to update SD control register: %d", err);
87 /* TODO: Convert to driver model */
88 static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
91 u8 ctrl_reg = AS3722_LDO_CONTROL0;
97 ctrl_reg = AS3722_LDO_CONTROL1;
101 err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
103 pr_err("failed to update LDO control register: %d", err);
110 int tegra_pcie_board_init(void)
115 ret = uclass_get_device_by_driver(UCLASS_PMIC,
116 DM_GET_DRIVER(pmic_as3722), &dev);
118 pr_err("failed to find AS3722 PMIC: %d\n", ret);
122 ret = as3722_sd_enable(dev, 4);
124 pr_err("failed to enable SD4: %d\n", ret);
128 ret = as3722_sd_set_voltage(dev, 4, 0x24);
130 pr_err("failed to set SD4 voltage: %d\n", ret);
134 gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
135 gpio_request(LAN_RESET_N, "LAN_RESET_N");
136 gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
138 #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
139 gpio_request(PEX_PERST_N, "PEX_PERST_N");
140 gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
141 #endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
146 void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
148 int index = tegra_pcie_port_index_of_port(port);
150 if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
154 ret = uclass_get_device_by_driver(UCLASS_PMIC,
155 DM_GET_DRIVER(pmic_as3722),
158 debug("%s: Failed to find PMIC\n", __func__);
162 /* Reset I210 Gigabit Ethernet Controller */
163 gpio_direction_output(LAN_RESET_N, 0);
166 * Make sure we don't get any back feeding from DEV_OFF_N resp.
169 gpio_direction_output(LAN_DEV_OFF_N, 0);
170 gpio_direction_output(LAN_WAKE_N, 0);
172 /* Make sure LDO9 and LDO10 are initially enabled @ 0V */
173 ret = as3722_ldo_enable(dev, 9);
175 pr_err("failed to enable LDO9: %d\n", ret);
178 ret = as3722_ldo_enable(dev, 10);
180 pr_err("failed to enable LDO10: %d\n", ret);
183 ret = as3722_ldo_set_voltage(dev, 9, 0x80);
185 pr_err("failed to set LDO9 voltage: %d\n", ret);
188 ret = as3722_ldo_set_voltage(dev, 10, 0x80);
190 pr_err("failed to set LDO10 voltage: %d\n", ret);
194 /* Make sure controller gets enabled by disabling DEV_OFF_N */
195 gpio_set_value(LAN_DEV_OFF_N, 1);
198 * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
199 * V1.0A and sample V1.0B and newer modules
201 ret = as3722_ldo_set_voltage(dev, 9, 0xff);
203 pr_err("failed to set LDO9 voltage: %d\n", ret);
206 ret = as3722_ldo_set_voltage(dev, 10, 0xff);
208 pr_err("failed to set LDO10 voltage: %d\n", ret);
213 * Must be asserted for 100 ms after power and clocks are stable
217 gpio_set_value(LAN_RESET_N, 1);
218 } else if (index == 0) { /* Apalis PCIe */
219 #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
221 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
224 gpio_direction_output(PEX_PERST_N, 0);
225 gpio_direction_output(RESET_MOCI_CTRL, 0);
228 * Must be asserted for 100 ms after power and clocks are stable
232 gpio_set_value(PEX_PERST_N, 1);
234 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
235 * Until 900 us After PEX_PERST# De-assertion
238 gpio_set_value(RESET_MOCI_CTRL, 1);
239 #endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
242 #endif /* CONFIG_PCI_TEGRA */