2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
7 * Refer docs/README.imxmage for more details about how-to configure
8 * and create imximage boot image
10 * The syntax is taken as close as possible with the kwbimage
29 #ifdef CONFIG_SECURE_BOOT
34 * Device Configuration Data (DCD)
36 * Each entry must have the format:
37 * Addr-type Address Value
40 * Addr-type register length (1,2 or 4 bytes)
41 * Address absolute address of the register
42 * value value to be stored in the register
46 DATA 4 0x30340004 0x4F400005
49 /* assuming MEMC_FREQ_RATIO = 2 */
51 DATA 4 0x30391000 0x00000002
53 DATA 4 0x307a0000 0x01040001
55 DATA 4 0x307a01a0 0x80400003
57 DATA 4 0x307a01a4 0x00100020
59 DATA 4 0x307a01a8 0x80100004
61 DATA 4 0x307a0064 0x00400045
63 DATA 4 0x307a0490 0x00000001
65 DATA 4 0x307a00d0 0x00020083
67 DATA 4 0x307a00d4 0x00690000
68 /* DDRC_INIT3 MR0/MR1 */
69 DATA 4 0x307a00dc 0x09300004
70 /* DDRC_INIT4 MR2/MR3 */
71 DATA 4 0x307a00e0 0x04480000
73 DATA 4 0x307a00e4 0x00100004
75 DATA 4 0x307a00f4 0x0000033f
77 DATA 4 0x307a0100 0x090b090a
79 DATA 4 0x307a0104 0x000d020d
81 DATA 4 0x307a0108 0x03040307
83 DATA 4 0x307a010c 0x00002006
85 DATA 4 0x307a0110 0x04020205
87 DATA 4 0x307a0114 0x03030202
89 DATA 4 0x307a0120 0x00000803
91 DATA 4 0x307a0180 0x00800020
93 DATA 4 0x307a0184 0x02001000
95 DATA 4 0x307a0190 0x02098204
97 DATA 4 0x307a0194 0x00030303
99 DATA 4 0x307a0200 0x0000001f
101 DATA 4 0x307a0204 0x00080808
103 DATA 4 0x307a0214 0x07070707
105 DATA 4 0x307a0218 0x07070707
107 DATA 4 0x307a0240 0x06000601
109 DATA 4 0x307a0244 0x00000011
111 DATA 4 0x30391000 0x00000000
112 /* DDR_PHY_PHY_CON0 */
113 DATA 4 0x30790000 0x17420f40
114 /* DDR_PHY_PHY_CON1 */
115 DATA 4 0x30790004 0x10210100
116 /* DDR_PHY_PHY_CON4 */
117 DATA 4 0x30790010 0x00060807
118 /* DDR_PHY_MDLL_CON0 */
119 DATA 4 0x307900b0 0x1010007e
120 /* DDR_PHY_DRVDS_CON0 */
121 DATA 4 0x3079009c 0x00000d6e
122 /* DDR_PHY_OFFSET_RD_CON0 */
123 DATA 4 0x30790020 0x08080808
124 /* DDR_PHY_OFFSET_WR_CON0 */
125 DATA 4 0x30790030 0x08080808
126 /* DDR_PHY_CMD_SDLL_CON0 */
127 DATA 4 0x30790050 0x01000010
128 DATA 4 0x30790050 0x00000010
130 /* DDR_PHY_ZQ_CON0 */
131 DATA 4 0x307900c0 0x0e407304
132 DATA 4 0x307900c0 0x0e447304
133 DATA 4 0x307900c0 0x0e447306
134 /* DDR_PHY_ZQ_CON1 */
135 CHECK_BITS_SET 4 0x307900c4 0x1
136 /* DDR_PHY_ZQ_CON0 */
137 DATA 4 0x307900c0 0x0e447304
138 DATA 4 0x307900c0 0x0e407304
141 DATA 4 0x30384130 0x00000000
142 /* IOMUXC_GPR_GPR8 */
143 DATA 4 0x30340020 0x00000178
145 DATA 4 0x30384130 0x00000002
146 /* DDR_PHY_LP_CON0 */
147 DATA 4 0x30790018 0x0000000f
150 CHECK_BITS_SET 4 0x307a0004 0x1