git.sur5r.net Git - u-boot/blob - board/toradex/colibri_vf/colibri_vf.c

   1 /*
   2  * Copyright 2015 Toradex, Inc.
   3  *
   4  * Based on vf610twr.c:
   5  * Copyright 2013 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux-vf610.h>
  14 #include <asm/arch/ddrmc-vf610.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/clock.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <miiphy.h>
  20 #include <netdev.h>
  21 #include <i2c.h>
  22 #include <g_dnl.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  27                         PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
  28
  29 #define ESDHC_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
  30                         PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
  31
  32 #define ENET_PAD_CTRL   (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
  33                         PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
  34
  35 int dram_init(void)
  36 {
  37         static const struct ddr3_jedec_timings timings = {
  38                 .tinit           = 5,
  39                 .trst_pwron      = 80000,
  40                 .cke_inactive    = 200000,
  41                 .wrlat           = 5,
  42                 .caslat_lin      = 12,
  43                 .trc             = 21,
  44                 .trrd            = 4,
  45                 .tccd            = 4,
  46                 .tfaw            = 20,
  47                 .trp             = 6,
  48                 .twtr            = 4,
  49                 .tras_min        = 15,
  50                 .tmrd            = 4,
  51                 .trtp            = 4,
  52                 .tras_max        = 28080,
  53                 .tmod            = 12,
  54                 .tckesr          = 4,
  55                 .tcke            = 3,
  56                 .trcd_int        = 6,
  57                 .tdal            = 12,
  58                 .tdll            = 512,
  59                 .trp_ab          = 6,
  60                 .tref            = 3120,
  61                 .trfc            = 64,
  62                 .tpdex           = 3,
  63                 .txpdll          = 10,
  64                 .txsnr           = 48,
  65                 .txsr            = 468,
  66                 .cksrx           = 5,
  67                 .cksre           = 5,
  68                 .zqcl            = 256,
  69                 .zqinit          = 512,
  70                 .zqcs            = 64,
  71                 .ref_per_zq      = 64,
  72                 .aprebit         = 10,
  73                 .wlmrd           = 40,
  74                 .wldqsen         = 25,
  75         };
  76
  77         ddrmc_setup_iomux();
  78
  79         ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2);
  80         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  81
  82         return 0;
  83 }
  84
  85 static void setup_iomux_uart(void)
  86 {
  87         static const iomux_v3_cfg_t uart_pads[] = {
  88                 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
  89                 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
  90                 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
  91                 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
  92         };
  93
  94         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  95 }
  96
  97 static void setup_iomux_enet(void)
  98 {
  99         static const iomux_v3_cfg_t enet0_pads[] = {
 100                 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
 101                 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
 102                 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
 103                 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
 104                 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
 105                 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
 106                 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
 107                 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
 108                 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
 109                 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
 110         };
 111
 112         imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
 113 }
 114
 115 static void setup_iomux_i2c(void)
 116 {
 117         static const iomux_v3_cfg_t i2c0_pads[] = {
 118                 VF610_PAD_PTB14__I2C0_SCL,
 119                 VF610_PAD_PTB15__I2C0_SDA,
 120         };
 121
 122         imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
 123 }
 124
 125 #ifdef CONFIG_NAND_VF610_NFC
 126 static void setup_iomux_nfc(void)
 127 {
 128         static const iomux_v3_cfg_t nfc_pads[] = {
 129                 VF610_PAD_PTD23__NF_IO7,
 130                 VF610_PAD_PTD22__NF_IO6,
 131                 VF610_PAD_PTD21__NF_IO5,
 132                 VF610_PAD_PTD20__NF_IO4,
 133                 VF610_PAD_PTD19__NF_IO3,
 134                 VF610_PAD_PTD18__NF_IO2,
 135                 VF610_PAD_PTD17__NF_IO1,
 136                 VF610_PAD_PTD16__NF_IO0,
 137                 VF610_PAD_PTB24__NF_WE_B,
 138                 VF610_PAD_PTB25__NF_CE0_B,
 139                 VF610_PAD_PTB27__NF_RE_B,
 140                 VF610_PAD_PTC26__NF_RB_B,
 141                 VF610_PAD_PTC27__NF_ALE,
 142                 VF610_PAD_PTC28__NF_CLE
 143         };
 144
 145         imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
 146 }
 147 #endif
 148
 149 #ifdef CONFIG_FSL_DSPI
 150 static void setup_iomux_dspi(void)
 151 {
 152         static const iomux_v3_cfg_t dspi1_pads[] = {
 153                 VF610_PAD_PTD5__DSPI1_CS0,
 154                 VF610_PAD_PTD6__DSPI1_SIN,
 155                 VF610_PAD_PTD7__DSPI1_SOUT,
 156                 VF610_PAD_PTD8__DSPI1_SCK,
 157         };
 158
 159         imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
 160 }
 161 #endif
 162
 163 #ifdef CONFIG_VYBRID_GPIO
 164 static void setup_iomux_gpio(void)
 165 {
 166         static const iomux_v3_cfg_t gpio_pads[] = {
 167                 VF610_PAD_PTA17__GPIO_7,
 168                 VF610_PAD_PTA20__GPIO_10,
 169                 VF610_PAD_PTA21__GPIO_11,
 170                 VF610_PAD_PTA30__GPIO_20,
 171                 VF610_PAD_PTA31__GPIO_21,
 172                 VF610_PAD_PTB0__GPIO_22,
 173                 VF610_PAD_PTB1__GPIO_23,
 174                 VF610_PAD_PTB6__GPIO_28,
 175                 VF610_PAD_PTB7__GPIO_29,
 176                 VF610_PAD_PTB8__GPIO_30,
 177                 VF610_PAD_PTB9__GPIO_31,
 178                 VF610_PAD_PTB12__GPIO_34,
 179                 VF610_PAD_PTB13__GPIO_35,
 180                 VF610_PAD_PTB16__GPIO_38,
 181                 VF610_PAD_PTB17__GPIO_39,
 182                 VF610_PAD_PTB18__GPIO_40,
 183                 VF610_PAD_PTB21__GPIO_43,
 184                 VF610_PAD_PTB22__GPIO_44,
 185                 VF610_PAD_PTC0__GPIO_45,
 186                 VF610_PAD_PTC1__GPIO_46,
 187                 VF610_PAD_PTC2__GPIO_47,
 188                 VF610_PAD_PTC3__GPIO_48,
 189                 VF610_PAD_PTC4__GPIO_49,
 190                 VF610_PAD_PTC5__GPIO_50,
 191                 VF610_PAD_PTC6__GPIO_51,
 192                 VF610_PAD_PTC7__GPIO_52,
 193                 VF610_PAD_PTC8__GPIO_53,
 194                 VF610_PAD_PTD31__GPIO_63,
 195                 VF610_PAD_PTD30__GPIO_64,
 196                 VF610_PAD_PTD29__GPIO_65,
 197                 VF610_PAD_PTD28__GPIO_66,
 198                 VF610_PAD_PTD27__GPIO_67,
 199                 VF610_PAD_PTD26__GPIO_68,
 200                 VF610_PAD_PTD25__GPIO_69,
 201                 VF610_PAD_PTD24__GPIO_70,
 202                 VF610_PAD_PTD9__GPIO_88,
 203                 VF610_PAD_PTD10__GPIO_89,
 204                 VF610_PAD_PTD11__GPIO_90,
 205                 VF610_PAD_PTD12__GPIO_91,
 206                 VF610_PAD_PTD13__GPIO_92,
 207                 VF610_PAD_PTB23__GPIO_93,
 208                 VF610_PAD_PTB26__GPIO_96,
 209                 VF610_PAD_PTB28__GPIO_98,
 210                 VF610_PAD_PTC29__GPIO_102,
 211                 VF610_PAD_PTC30__GPIO_103,
 212                 VF610_PAD_PTA7__GPIO_134,
 213         };
 214
 215         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 216 }
 217 #endif
 218
 219 #ifdef CONFIG_FSL_ESDHC
 220 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 221         {ESDHC1_BASE_ADDR},
 222 };
 223
 224 int board_mmc_getcd(struct mmc *mmc)
 225 {
 226         /* eSDHC1 is always present */
 227         return 1;
 228 }
 229
 230 int board_mmc_init(bd_t *bis)
 231 {
 232         static const iomux_v3_cfg_t esdhc1_pads[] = {
 233                 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
 234                 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
 235                 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
 236                 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
 237                 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
 238                 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
 239         };
 240
 241         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 242
 243         imx_iomux_v3_setup_multiple_pads(
 244                 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
 245
 246         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 247 }
 248 #endif
 249
 250 static inline int is_colibri_vf61(void)
 251 {
 252         struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
 253
 254         /*
 255          * Detect board type by Level 2 Cache: VF50 don't have any
 256          * Level 2 Cache.
 257          */
 258         return !!mscm->cpxcfg1;
 259 }
 260
 261 static void clock_init(void)
 262 {
 263         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 264         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 265         u32 pfd_clk_sel, ddr_clk_sel;
 266
 267         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 268                         CCM_CCGR0_UART0_CTRL_MASK);
 269 #ifdef CONFIG_FSL_DSPI
 270         setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
 271 #endif
 272         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 273                         CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 274         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 275                         CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 276                         CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
 277                         CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
 278         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 279                         CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
 280         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 281                         CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 282                         CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
 283         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 284                         CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 285         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 286                         CCM_CCGR7_SDHC1_CTRL_MASK);
 287         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 288                         CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 289         clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
 290                         CCM_CCGR10_NFC_CTRL_MASK);
 291
 292 #ifdef CONFIG_CI_UDC
 293         setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
 294 #endif
 295
 296 #ifdef CONFIG_USB_EHCI
 297         setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
 298 #endif
 299
 300         clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
 301                         ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
 302                         ANADIG_PLL5_CTRL_DIV_SELECT);
 303
 304         if (is_colibri_vf61()) {
 305                 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
 306                                 ANADIG_PLL2_CTRL_POWERDOWN,
 307                                 ANADIG_PLL2_CTRL_ENABLE |
 308                                 ANADIG_PLL2_CTRL_DIV_SELECT);
 309         }
 310
 311         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 312                         ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 313
 314         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 315                         CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
 316
 317         /* See "Typical PLL Configuration" */
 318         if (is_colibri_vf61()) {
 319                 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
 320                 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
 321         } else {
 322                 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
 323                 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
 324         }
 325
 326         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
 327                         CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
 328                         CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
 329                         CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
 330                         CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
 331                         ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
 332                         CCM_CCSR_SYS_CLK_SEL(4));
 333
 334         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 335                         CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 336                         CCM_CACRR_ARM_CLK_DIV(0));
 337         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
 338                         CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
 339                         CCM_CSCMR1_NFC_CLK_SEL(0));
 340         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 341                         CCM_CSCDR1_RMII_CLK_EN);
 342         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 343                         CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
 344                         CCM_CSCDR2_NFC_EN);
 345         clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
 346                         CCM_CSCDR3_NFC_PRE_DIV(5));
 347         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 348                         CCM_CSCMR2_RMII_CLK_SEL(2));
 349 }
 350
 351 static void mscm_init(void)
 352 {
 353         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
 354         int i;
 355
 356         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
 357                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 358 }
 359
 360 int board_phy_config(struct phy_device *phydev)
 361 {
 362         if (phydev->drv->config)
 363                 phydev->drv->config(phydev);
 364
 365         return 0;
 366 }
 367
 368 int board_early_init_f(void)
 369 {
 370         clock_init();
 371         mscm_init();
 372
 373         setup_iomux_uart();
 374         setup_iomux_enet();
 375         setup_iomux_i2c();
 376 #ifdef CONFIG_NAND_VF610_NFC
 377         setup_iomux_nfc();
 378 #endif
 379
 380 #ifdef CONFIG_VYBRID_GPIO
 381         setup_iomux_gpio();
 382 #endif
 383
 384 #ifdef CONFIG_FSL_DSPI
 385         setup_iomux_dspi();
 386 #endif
 387
 388         return 0;
 389 }
 390
 391 #ifdef CONFIG_BOARD_LATE_INIT
 392 int board_late_init(void)
 393 {
 394         struct src *src = (struct src *)SRC_BASE_ADDR;
 395
 396         /* Default memory arguments */
 397         if (!getenv("memargs")) {
 398                 switch (gd->ram_size) {
 399                 case 0x08000000:
 400                         /* 128 MB */
 401                         setenv("memargs", "mem=128M");
 402                         break;
 403                 case 0x10000000:
 404                         /* 256 MB */
 405                         setenv("memargs", "mem=256M");
 406                         break;
 407                 default:
 408                         printf("Failed detecting RAM size.\n");
 409                 }
 410         }
 411
 412         if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
 413                         == SRC_SBMR2_BMOD_SERIAL) {
 414                 printf("Serial Downloader recovery mode, disable autoboot\n");
 415                 setenv("bootdelay", "-1");
 416         }
 417
 418         return 0;
 419 }
 420 #endif /* CONFIG_BOARD_LATE_INIT */
 421
 422 int board_init(void)
 423 {
 424         struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
 425
 426         /* address of boot parameters */
 427         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 428
 429         /*
 430          * Enable external 32K Oscillator
 431          *
 432          * The internal clock experiences significant drift
 433          * so we must use the external oscillator in order
 434          * to maintain correct time in the hwclock
 435          */
 436
 437         setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
 438
 439         return 0;
 440 }
 441
 442 int checkboard(void)
 443 {
 444         if (is_colibri_vf61())
 445                 puts("Board: Colibri VF61\n");
 446         else
 447                 puts("Board: Colibri VF50\n");
 448
 449         return 0;
 450 }
 451
 452 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 453 {
 454         unsigned short usb_pid;
 455
 456         put_unaligned(CONFIG_TRDX_VID, &dev->idVendor);
 457
 458         if (is_colibri_vf61())
 459                 usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT;
 460         else
 461                 usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT;
 462
 463         put_unaligned(usb_pid, &dev->idProduct);
 464
 465         return 0;
 466 }