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colibri_vf: usb gadget: toradex pid is now set generically
[u-boot] / board / toradex / colibri_vf / colibri_vf.c
1 /*
2  * Copyright 2015 Toradex, Inc.
3  *
4  * Based on vf610twr.c:
5  * Copyright 2013 Freescale Semiconductor, Inc.
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <asm/io.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux-vf610.h>
14 #include <asm/arch/ddrmc-vf610.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
17 #include <mmc.h>
18 #include <fsl_esdhc.h>
19 #include <miiphy.h>
20 #include <netdev.h>
21 #include <i2c.h>
22 #include <g_dnl.h>
23 #include <asm/gpio.h>
24 #include <usb.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
29                         PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
30
31 #define ESDHC_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
32                         PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
33
34 #define ENET_PAD_CTRL   (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
35                         PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
36
37 #define USB_PEN_GPIO           83
38 #define USB_CDET_GPIO           102
39
40 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
41         /* levelling */
42         { DDRMC_CR97_WRLVL_EN, 97 },
43         { DDRMC_CR98_WRLVL_DL_0(0), 98 },
44         { DDRMC_CR99_WRLVL_DL_1(0), 99 },
45         { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
46         { DDRMC_CR105_RDLVL_DL_0(0), 105 },
47         { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
48         { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
49         /* AXI */
50         { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
51         { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
52         { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
53                    DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
54         { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
55                    DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
56         { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
57                    DDRMC_CR122_AXI0_PRIRLX(100), 122 },
58         { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
59                    DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
60         { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
61         { DDRMC_CR126_PHY_RDLAT(8), 126 },
62         { DDRMC_CR132_WRLAT_ADJ(5) |
63                    DDRMC_CR132_RDLAT_ADJ(6), 132 },
64         { DDRMC_CR137_PHYCTL_DL(2), 137 },
65         { DDRMC_CR138_PHY_WRLV_MXDL(256) |
66                    DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
67         { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
68                    DDRMC_CR139_PHY_WRLV_DLL(3) |
69                    DDRMC_CR139_PHY_WRLV_EN(3), 139 },
70         { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
71         { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
72                    DDRMC_CR143_RDLV_MXDL(128), 143 },
73         { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
74                    DDRMC_CR144_PHY_RDLV_DLL(3) |
75                    DDRMC_CR144_PHY_RDLV_EN(3), 144 },
76         { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
77         { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
78         { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
79         { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
80         { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
81                    DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
82
83         { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
84                    DDRMC_CR154_PAD_ZQ_MODE(1) |
85                    DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
86                    DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
87         { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
88         { DDRMC_CR158_TWR(6), 158 },
89         { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
90                    DDRMC_CR161_TODTH_WR(2), 161 },
91         /* end marker */
92         { 0, -1 }
93 };
94
95 static const iomux_v3_cfg_t usb_pads[] = {
96         VF610_PAD_PTD4__GPIO_83,
97         VF610_PAD_PTC29__GPIO_102,
98 };
99
100 int dram_init(void)
101 {
102         static const struct ddr3_jedec_timings timings = {
103                 .tinit             = 5,
104                 .trst_pwron        = 80000,
105                 .cke_inactive      = 200000,
106                 .wrlat             = 5,
107                 .caslat_lin        = 12,
108                 .trc               = 21,
109                 .trrd              = 4,
110                 .tccd              = 4,
111                 .tbst_int_interval = 0,
112                 .tfaw              = 20,
113                 .trp               = 6,
114                 .twtr              = 4,
115                 .tras_min          = 15,
116                 .tmrd              = 4,
117                 .trtp              = 4,
118                 .tras_max          = 28080,
119                 .tmod              = 12,
120                 .tckesr            = 4,
121                 .tcke              = 3,
122                 .trcd_int          = 6,
123                 .tras_lockout      = 0,
124                 .tdal              = 12,
125                 .bstlen            = 3,
126                 .tdll              = 512,
127                 .trp_ab            = 6,
128                 .tref              = 3120,
129                 .trfc              = 64,
130                 .tref_int          = 0,
131                 .tpdex             = 3,
132                 .txpdll            = 10,
133                 .txsnr             = 48,
134                 .txsr              = 468,
135                 .cksrx             = 5,
136                 .cksre             = 5,
137                 .freq_chg_en       = 0,
138                 .zqcl              = 256,
139                 .zqinit            = 512,
140                 .zqcs              = 64,
141                 .ref_per_zq        = 64,
142                 .zqcs_rotate       = 0,
143                 .aprebit           = 10,
144                 .cmd_age_cnt       = 64,
145                 .age_cnt           = 64,
146                 .q_fullness        = 7,
147                 .odt_rd_mapcs0     = 0,
148                 .odt_wr_mapcs0     = 1,
149                 .wlmrd             = 40,
150                 .wldqsen           = 25,
151         };
152
153         ddrmc_setup_iomux(NULL, 0);
154
155         ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
156         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
157
158         return 0;
159 }
160
161 static void setup_iomux_uart(void)
162 {
163         static const iomux_v3_cfg_t uart_pads[] = {
164                 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
165                 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
166                 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
167                 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
168         };
169
170         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
171 }
172
173 static void setup_iomux_enet(void)
174 {
175         static const iomux_v3_cfg_t enet0_pads[] = {
176                 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
177                 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
178                 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
179                 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
180                 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
181                 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
182                 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
183                 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
184                 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
185                 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
186         };
187
188         imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
189 }
190
191 static void setup_iomux_i2c(void)
192 {
193         static const iomux_v3_cfg_t i2c0_pads[] = {
194                 VF610_PAD_PTB14__I2C0_SCL,
195                 VF610_PAD_PTB15__I2C0_SDA,
196         };
197
198         imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
199 }
200
201 #ifdef CONFIG_NAND_VF610_NFC
202 static void setup_iomux_nfc(void)
203 {
204         static const iomux_v3_cfg_t nfc_pads[] = {
205                 VF610_PAD_PTD23__NF_IO7,
206                 VF610_PAD_PTD22__NF_IO6,
207                 VF610_PAD_PTD21__NF_IO5,
208                 VF610_PAD_PTD20__NF_IO4,
209                 VF610_PAD_PTD19__NF_IO3,
210                 VF610_PAD_PTD18__NF_IO2,
211                 VF610_PAD_PTD17__NF_IO1,
212                 VF610_PAD_PTD16__NF_IO0,
213                 VF610_PAD_PTB24__NF_WE_B,
214                 VF610_PAD_PTB25__NF_CE0_B,
215                 VF610_PAD_PTB27__NF_RE_B,
216                 VF610_PAD_PTC26__NF_RB_B,
217                 VF610_PAD_PTC27__NF_ALE,
218                 VF610_PAD_PTC28__NF_CLE
219         };
220
221         imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
222 }
223 #endif
224
225 #ifdef CONFIG_FSL_DSPI
226 static void setup_iomux_dspi(void)
227 {
228         static const iomux_v3_cfg_t dspi1_pads[] = {
229                 VF610_PAD_PTD5__DSPI1_CS0,
230                 VF610_PAD_PTD6__DSPI1_SIN,
231                 VF610_PAD_PTD7__DSPI1_SOUT,
232                 VF610_PAD_PTD8__DSPI1_SCK,
233         };
234
235         imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
236 }
237 #endif
238
239 #ifdef CONFIG_VYBRID_GPIO
240 static void setup_iomux_gpio(void)
241 {
242         static const iomux_v3_cfg_t gpio_pads[] = {
243                 VF610_PAD_PTA17__GPIO_7,
244                 VF610_PAD_PTA20__GPIO_10,
245                 VF610_PAD_PTA21__GPIO_11,
246                 VF610_PAD_PTA30__GPIO_20,
247                 VF610_PAD_PTA31__GPIO_21,
248                 VF610_PAD_PTB0__GPIO_22,
249                 VF610_PAD_PTB1__GPIO_23,
250                 VF610_PAD_PTB6__GPIO_28,
251                 VF610_PAD_PTB7__GPIO_29,
252                 VF610_PAD_PTB8__GPIO_30,
253                 VF610_PAD_PTB9__GPIO_31,
254                 VF610_PAD_PTB12__GPIO_34,
255                 VF610_PAD_PTB13__GPIO_35,
256                 VF610_PAD_PTB16__GPIO_38,
257                 VF610_PAD_PTB17__GPIO_39,
258                 VF610_PAD_PTB18__GPIO_40,
259                 VF610_PAD_PTB21__GPIO_43,
260                 VF610_PAD_PTB22__GPIO_44,
261                 VF610_PAD_PTC0__GPIO_45,
262                 VF610_PAD_PTC1__GPIO_46,
263                 VF610_PAD_PTC2__GPIO_47,
264                 VF610_PAD_PTC3__GPIO_48,
265                 VF610_PAD_PTC4__GPIO_49,
266                 VF610_PAD_PTC5__GPIO_50,
267                 VF610_PAD_PTC6__GPIO_51,
268                 VF610_PAD_PTC7__GPIO_52,
269                 VF610_PAD_PTC8__GPIO_53,
270                 VF610_PAD_PTD31__GPIO_63,
271                 VF610_PAD_PTD30__GPIO_64,
272                 VF610_PAD_PTD29__GPIO_65,
273                 VF610_PAD_PTD28__GPIO_66,
274                 VF610_PAD_PTD27__GPIO_67,
275                 VF610_PAD_PTD26__GPIO_68,
276                 VF610_PAD_PTD25__GPIO_69,
277                 VF610_PAD_PTD24__GPIO_70,
278                 VF610_PAD_PTD9__GPIO_88,
279                 VF610_PAD_PTD10__GPIO_89,
280                 VF610_PAD_PTD11__GPIO_90,
281                 VF610_PAD_PTD12__GPIO_91,
282                 VF610_PAD_PTD13__GPIO_92,
283                 VF610_PAD_PTB23__GPIO_93,
284                 VF610_PAD_PTB26__GPIO_96,
285                 VF610_PAD_PTB28__GPIO_98,
286                 VF610_PAD_PTC30__GPIO_103,
287                 VF610_PAD_PTA7__GPIO_134,
288         };
289
290         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
291 }
292 #endif
293
294 #ifdef CONFIG_FSL_ESDHC
295 struct fsl_esdhc_cfg esdhc_cfg[1] = {
296         {ESDHC1_BASE_ADDR},
297 };
298
299 int board_mmc_getcd(struct mmc *mmc)
300 {
301         /* eSDHC1 is always present */
302         return 1;
303 }
304
305 int board_mmc_init(bd_t *bis)
306 {
307         static const iomux_v3_cfg_t esdhc1_pads[] = {
308                 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
309                 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
310                 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
311                 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
312                 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
313                 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
314         };
315
316         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
317
318         imx_iomux_v3_setup_multiple_pads(
319                 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
320
321         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
322 }
323 #endif
324
325 static inline int is_colibri_vf61(void)
326 {
327         struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
328
329         /*
330          * Detect board type by Level 2 Cache: VF50 don't have any
331          * Level 2 Cache.
332          */
333         return !!mscm->cpxcfg1;
334 }
335
336 static void clock_init(void)
337 {
338         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
339         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
340         u32 pfd_clk_sel, ddr_clk_sel;
341
342         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
343                         CCM_CCGR0_UART0_CTRL_MASK);
344 #ifdef CONFIG_FSL_DSPI
345         setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
346 #endif
347         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
348                         CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
349         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
350                         CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
351                         CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
352                         CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
353         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
354                         CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
355         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
356                         CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
357                         CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
358         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
359                         CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
360         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
361                         CCM_CCGR7_SDHC1_CTRL_MASK);
362         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
363                         CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
364         clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
365                         CCM_CCGR10_NFC_CTRL_MASK);
366
367 #ifdef CONFIG_CI_UDC
368         setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
369 #endif
370
371 #ifdef CONFIG_USB_EHCI
372         setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
373 #endif
374
375         clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
376                         ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
377                         ANADIG_PLL5_CTRL_DIV_SELECT);
378
379         if (is_colibri_vf61()) {
380                 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
381                                 ANADIG_PLL2_CTRL_POWERDOWN,
382                                 ANADIG_PLL2_CTRL_ENABLE |
383                                 ANADIG_PLL2_CTRL_DIV_SELECT);
384         }
385
386         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
387                         ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
388
389         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
390                         CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
391
392         /* See "Typical PLL Configuration" */
393         if (is_colibri_vf61()) {
394                 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
395                 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
396         } else {
397                 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
398                 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
399         }
400
401         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
402                         CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
403                         CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
404                         CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
405                         CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
406                         ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
407                         CCM_CCSR_SYS_CLK_SEL(4));
408
409         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
410                         CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
411                         CCM_CACRR_ARM_CLK_DIV(0));
412         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
413                         CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
414                         CCM_CSCMR1_NFC_CLK_SEL(0));
415         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
416                         CCM_CSCDR1_RMII_CLK_EN);
417         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
418                         CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
419                         CCM_CSCDR2_NFC_EN);
420         clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
421                         CCM_CSCDR3_NFC_PRE_DIV(5));
422         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
423                         CCM_CSCMR2_RMII_CLK_SEL(2));
424 }
425
426 static void mscm_init(void)
427 {
428         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
429         int i;
430
431         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
432                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
433 }
434
435 int board_phy_config(struct phy_device *phydev)
436 {
437         if (phydev->drv->config)
438                 phydev->drv->config(phydev);
439
440         return 0;
441 }
442
443 int board_early_init_f(void)
444 {
445         clock_init();
446         mscm_init();
447
448         setup_iomux_uart();
449         setup_iomux_enet();
450         setup_iomux_i2c();
451 #ifdef CONFIG_NAND_VF610_NFC
452         setup_iomux_nfc();
453 #endif
454
455 #ifdef CONFIG_VYBRID_GPIO
456         setup_iomux_gpio();
457 #endif
458
459 #ifdef CONFIG_FSL_DSPI
460         setup_iomux_dspi();
461 #endif
462
463         return 0;
464 }
465
466 #ifdef CONFIG_BOARD_LATE_INIT
467 int board_late_init(void)
468 {
469         struct src *src = (struct src *)SRC_BASE_ADDR;
470
471         /* Default memory arguments */
472         if (!getenv("memargs")) {
473                 switch (gd->ram_size) {
474                 case 0x08000000:
475                         /* 128 MB */
476                         setenv("memargs", "mem=128M");
477                         break;
478                 case 0x10000000:
479                         /* 256 MB */
480                         setenv("memargs", "mem=256M");
481                         break;
482                 default:
483                         printf("Failed detecting RAM size.\n");
484                 }
485         }
486
487         if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
488                         == SRC_SBMR2_BMOD_SERIAL) {
489                 printf("Serial Downloader recovery mode, disable autoboot\n");
490                 setenv("bootdelay", "-1");
491         }
492
493         return 0;
494 }
495 #endif /* CONFIG_BOARD_LATE_INIT */
496
497 int board_init(void)
498 {
499         struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
500
501         /* address of boot parameters */
502         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
503
504         /*
505          * Enable external 32K Oscillator
506          *
507          * The internal clock experiences significant drift
508          * so we must use the external oscillator in order
509          * to maintain correct time in the hwclock
510          */
511
512         setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
513
514 #ifdef CONFIG_USB_EHCI_VF
515         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
516 #endif
517
518         return 0;
519 }
520
521 int checkboard(void)
522 {
523         if (is_colibri_vf61())
524                 puts("Board: Colibri VF61\n");
525         else
526                 puts("Board: Colibri VF50\n");
527
528         return 0;
529 }
530
531 #ifdef CONFIG_USB_EHCI_VF
532 int board_ehci_hcd_init(int port)
533 {
534         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
535
536         switch (port) {
537         case 0:
538                 /* USBC does not have PEN, also configured as USB client only */
539                 break;
540         case 1:
541                 gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
542                 gpio_direction_output(USB_PEN_GPIO, 0);
543                 break;
544         }
545         return 0;
546 }
547
548 int board_usb_phy_mode(int port)
549 {
550         switch (port) {
551         case 0:
552                 /*
553                  * Port 0 is used only in client mode on Colibri Vybrid modules
554                  * Check for state of USB client gpio pin and accordingly return
555                  * USB_INIT_DEVICE or USB_INIT_HOST.
556                  */
557                 if (gpio_get_value(USB_CDET_GPIO))
558                         return USB_INIT_DEVICE;
559                 else
560                         return USB_INIT_HOST;
561         case 1:
562                 /* Port 1 is used only in host mode on Colibri Vybrid modules */
563                 return USB_INIT_HOST;
564         default:
565                 /*
566                  * There are only two USB controllers on Vybrid. Ideally we will
567                  * not reach here. However return USB_INIT_HOST if we do.
568                  */
569                 return USB_INIT_HOST;
570         }
571 }
572 #endif