2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
8 * SPDX-License-Identifier: GPL-2.0+
16 #ifndef CONFIG_SYS_RAMBOOT
17 static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
19 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
21 /* unlock mode register */
22 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit;
23 __asm__ volatile ("sync");
25 /* precharge all banks */
26 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
27 __asm__ volatile ("sync");
29 if (sdram_conf->ddr) {
30 /* set mode register: extended mode */
31 *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode;
32 __asm__ volatile ("sync");
34 /* set mode register: reset DLL */
35 *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000;
36 __asm__ volatile ("sync");
39 /* precharge all banks */
40 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
41 __asm__ volatile ("sync");
44 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit;
45 __asm__ volatile ("sync");
47 /* set mode register */
48 *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode;
49 __asm__ volatile ("sync");
51 /* normal operation */
52 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit;
53 __asm__ volatile ("sync");
58 * ATTENTION: Although partially referenced initdram does NOT make real use
59 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
60 * is something else than 0x00000000.
63 long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
67 #ifndef CONFIG_SYS_RAMBOOT
70 /* setup SDRAM chip selects */
71 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
72 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
73 __asm__ volatile ("sync");
75 /* setup config registers */
76 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
77 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
78 __asm__ volatile ("sync");
80 if (sdram_conf->ddr) {
82 *(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
83 __asm__ volatile ("sync");
86 /* find RAM size using SDRAM CS0 only */
87 mpc5xxx_sdram_start(sdram_conf, 0);
88 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
89 mpc5xxx_sdram_start(sdram_conf, 1);
90 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
92 mpc5xxx_sdram_start(sdram_conf, 0);
98 /* memory smaller than 1MB is impossible */
99 if (dramsize < (1 << 20)) {
103 /* set SDRAM CS0 size according to the amount of RAM found */
105 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
107 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
110 /* let SDRAM CS1 start right after CS0 */
111 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
113 /* find RAM size using SDRAM CS1 only */
114 mpc5xxx_sdram_start(sdram_conf, 0);
115 test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
116 mpc5xxx_sdram_start(sdram_conf, 1);
117 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
119 mpc5xxx_sdram_start(sdram_conf, 0);
125 /* memory smaller than 1MB is impossible */
126 if (dramsize2 < (1 << 20)) {
130 /* set SDRAM CS1 size according to the amount of RAM found */
132 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
133 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
135 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
138 #else /* CONFIG_SYS_RAMBOOT */
140 /* retrieve size of memory connected to SDRAM CS0 */
141 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
142 if (dramsize >= 0x13) {
143 dramsize = (1 << (dramsize - 0x13)) << 20;
148 /* retrieve size of memory connected to SDRAM CS1 */
149 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
150 if (dramsize2 >= 0x13) {
151 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
156 #endif /* CONFIG_SYS_RAMBOOT */
158 return dramsize + dramsize2;