2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/processor.h>
21 #ifdef CONFIG_VIDEO_SM501
25 #if defined(CONFIG_MPC5200_DDR)
26 #include "mt46v16m16-75.h"
28 #include "mt48lc16m16a2-75.h"
31 #ifdef CONFIG_OF_LIBFDT
32 #include <fdt_support.h>
33 #endif /* CONFIG_OF_LIBFDT */
35 DECLARE_GLOBAL_DATA_PTR;
38 void ps2mult_early_init(void);
41 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
44 * EDID block has been generated using Phoenix EDID Designer 1.3.
45 * This tool creates a text file containing:
49 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
50 * ------------------------------------------------
51 * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
52 * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
53 * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
54 * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
55 * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
56 * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
57 * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
58 * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
60 * Then this data has been manually converted to the char
63 static unsigned char edid_buf[128] = {
64 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
65 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
66 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
68 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
69 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
70 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
71 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
73 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
74 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
75 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
76 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
78 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
83 #ifndef CONFIG_SYS_RAMBOOT
84 static void sdram_start (int hi_addr)
86 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
88 /* unlock mode register */
89 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
91 __asm__ volatile ("sync");
93 /* precharge all banks */
94 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
96 __asm__ volatile ("sync");
99 /* set mode register: extended mode */
100 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
101 __asm__ volatile ("sync");
103 /* set mode register: reset DLL */
104 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
105 __asm__ volatile ("sync");
108 /* precharge all banks */
109 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
111 __asm__ volatile ("sync");
114 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
116 __asm__ volatile ("sync");
118 /* set mode register */
119 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
120 __asm__ volatile ("sync");
122 /* normal operation */
123 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
124 __asm__ volatile ("sync");
129 * ATTENTION: Although partially referenced initdram does NOT make real use
130 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
131 * is something else than 0x00000000.
134 phys_size_t initdram (int board_type)
140 #ifndef CONFIG_SYS_RAMBOOT
143 /* setup SDRAM chip selects */
144 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
145 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
146 __asm__ volatile ("sync");
148 /* setup config registers */
149 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
150 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
151 __asm__ volatile ("sync");
155 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
156 __asm__ volatile ("sync");
159 /* find RAM size using SDRAM CS0 only */
161 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
163 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
171 /* memory smaller than 1MB is impossible */
172 if (dramsize < (1 << 20)) {
176 /* set SDRAM CS0 size according to the amount of RAM found */
178 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
179 __builtin_ffs(dramsize >> 20) - 1;
181 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
184 /* let SDRAM CS1 start right after CS0 */
185 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
187 /* find RAM size using SDRAM CS1 only */
190 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
193 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
202 /* memory smaller than 1MB is impossible */
203 if (dramsize2 < (1 << 20)) {
207 /* set SDRAM CS1 size according to the amount of RAM found */
209 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
210 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
212 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
215 #else /* CONFIG_SYS_RAMBOOT */
217 /* retrieve size of memory connected to SDRAM CS0 */
218 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
219 if (dramsize >= 0x13) {
220 dramsize = (1 << (dramsize - 0x13)) << 20;
225 /* retrieve size of memory connected to SDRAM CS1 */
226 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
227 if (dramsize2 >= 0x13) {
228 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
232 #endif /* CONFIG_SYS_RAMBOOT */
235 * On MPC5200B we need to set the special configuration delay in the
236 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
237 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
239 * "The SDelay should be written to a value of 0x00000004. It is
240 * required to account for changes caused by normal wafer processing
245 if ((SVR_MJREV(svr) >= 2) &&
246 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
248 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
249 __asm__ volatile ("sync");
252 #if defined(CONFIG_TQM5200_B)
253 return dramsize + dramsize2;
256 #endif /* CONFIG_TQM5200_B */
259 int checkboard (void)
261 #if defined(CONFIG_TQM5200S)
262 # define MODULE_NAME "TQM5200S"
264 # define MODULE_NAME "TQM5200"
267 #if defined(CONFIG_STK52XX)
268 # define CARRIER_NAME "STK52xx"
269 #elif defined(CONFIG_CAM5200)
270 # define CARRIER_NAME "CAM5200"
271 #elif defined(CONFIG_FO300)
272 # define CARRIER_NAME "FO300"
273 #elif defined(CONFIG_CHARON)
274 # define CARRIER_NAME "CHARON"
279 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
280 " on a " CARRIER_NAME " carrier board\n");
288 void flash_preinit(void)
291 * Now, when we are in RAM, enable flash write
292 * access for detection process.
293 * Note that CS_BOOT cannot be cleared when
294 * executing in flash.
296 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
301 static struct pci_controller hose;
303 extern void pci_mpc5xxx_init(struct pci_controller *);
305 void pci_init_board(void)
307 pci_mpc5xxx_init(&hose);
311 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
313 #if defined (CONFIG_MINIFAP)
314 #define SM501_POWER_MODE0_GATE 0x00000040UL
315 #define SM501_POWER_MODE1_GATE 0x00000048UL
316 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
317 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
318 #define SM501_GPIO_DATA_HIGH 0x00010004UL
319 #define SM501_GPIO_51 0x00080000UL
320 #endif /* CONFIG MINIFAP */
322 void init_ide_reset (void)
324 debug ("init_ide_reset\n");
326 #if defined (CONFIG_MINIFAP)
327 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
329 /* enable GPIO control (in both power modes) */
330 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
331 POWER_MODE_GATE_GPIO_PWM_I2C;
332 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
333 POWER_MODE_GATE_GPIO_PWM_I2C;
334 /* configure GPIO51 as output */
335 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
338 /* Configure PSC1_4 as GPIO output for ATA reset */
339 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
340 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
342 /* by default the ATA reset is de-asserted */
343 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
347 void ide_set_reset (int idereset)
349 debug ("ide_reset(%d)\n", idereset);
351 #if defined (CONFIG_MINIFAP)
353 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
356 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
361 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
363 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
371 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
372 * is left open, no keypress is detected.
374 int post_hotkeys_pressed(void)
376 #ifdef CONFIG_STK52XX
377 struct mpc5xxx_gpio *gpio;
379 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
382 * Configure PSC6_0 through PSC6_3 as GPIO.
384 gpio->port_config &= ~(0x00700000);
386 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
387 gpio->simple_gpioe |= 0x20000000;
389 /* Configure GPIO_IRDA_1 as input */
390 gpio->simple_ddr &= ~(0x20000000);
392 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
399 #ifdef CONFIG_BOARD_EARLY_INIT_R
400 int board_early_init_r (void)
403 extern int usb_cpu_init(void);
405 #ifdef CONFIG_PS2MULT
406 ps2mult_early_init();
407 #endif /* CONFIG_PS2MULT */
409 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
410 /* Low level USB init, required for proper kernel operation */
419 int silent_boot (void)
421 vu_long timer3_status;
423 /* Configure GPT3 as GPIO input */
424 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
426 /* Read in TIMER_3 pin status */
427 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
429 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
430 /* Force silent console mode if S1 switch
431 * is in closed position (TIMER_3 pin status is LOW). */
432 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
435 /* Force silent console mode if S1 switch
436 * is in open position (TIMER_3 pin status is HIGH). */
437 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
444 int board_early_init_f (void)
447 gd->flags |= GD_FLG_SILENT;
451 #endif /* CONFIG_FO300 */
453 #if defined(CONFIG_CHARON)
457 /* The TFP410 registers */
458 #define TFP410_REG_VEN_ID_L 0x00
459 #define TFP410_REG_VEN_ID_H 0x01
460 #define TFP410_REG_DEV_ID_L 0x02
461 #define TFP410_REG_DEV_ID_H 0x03
462 #define TFP410_REG_REV_ID 0x04
464 #define TFP410_REG_CTL_1_MODE 0x08
465 #define TFP410_REG_CTL_2_MODE 0x09
466 #define TFP410_REG_CTL_3_MODE 0x0A
468 #define TFP410_REG_CFG 0x0B
470 #define TFP410_REG_DE_DLY 0x32
471 #define TFP410_REG_DE_CTL 0x33
472 #define TFP410_REG_DE_TOP 0x34
473 #define TFP410_REG_DE_CNT_L 0x36
474 #define TFP410_REG_DE_CNT_H 0x37
475 #define TFP410_REG_DE_LIN_L 0x38
476 #define TFP410_REG_DE_LIN_H 0x39
478 #define TFP410_REG_H_RES_L 0x3A
479 #define TFP410_REG_H_RES_H 0x3B
480 #define TFP410_REG_V_RES_L 0x3C
481 #define TFP410_REG_V_RES_H 0x3D
483 static int tfp410_read_reg(int reg, uchar *buf)
485 if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
486 puts ("Error reading the chip.\n");
492 static int tfp410_write_reg(int reg, uchar buf)
494 if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
495 puts ("Error writing the chip.\n");
501 typedef struct _tfp410_config {
506 static TFP410_CONFIG tfp410_configtbl[] = {
507 {TFP410_REG_CTL_1_MODE, 0x37},
508 {TFP410_REG_CTL_2_MODE, 0x20},
509 {TFP410_REG_CTL_3_MODE, 0x80},
510 {TFP410_REG_DE_DLY, 0x90},
511 {TFP410_REG_DE_CTL, 0x00},
512 {TFP410_REG_DE_TOP, 0x23},
513 {TFP410_REG_DE_CNT_H, 0x02},
514 {TFP410_REG_DE_CNT_L, 0x80},
515 {TFP410_REG_DE_LIN_H, 0x01},
516 {TFP410_REG_DE_LIN_L, 0xe0},
520 static int charon_last_stage_init(void)
522 volatile struct mpc5xxx_lpb *lpb =
523 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
524 int oldbus = i2c_get_bus_num();
528 i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
531 if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
535 if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
539 /* OK, now init the chip */
540 while (tfp410_configtbl[i].reg != -1) {
543 ret = tfp410_write_reg(tfp410_configtbl[i].reg,
544 tfp410_configtbl[i].val);
549 printf("TFP410 initialized.\n");
550 i2c_set_bus_num(oldbus);
552 /* set deadcycle for cs3 to 0 */
553 setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
558 int last_stage_init (void)
561 * auto scan for really existing devices and re-set chip select
568 * Check for SRAM and SRAM size
571 /* save original SRAM content */
572 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
575 /* write test pattern to SRAM */
576 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
577 __asm__ volatile ("sync");
579 * Put a different pattern on the data lines: otherwise they may float
580 * long enough to read back what we wrote.
582 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
584 puts ("!! possible error in SRAM detection\n");
586 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
587 /* no SRAM at all, disable cs */
588 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
589 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
590 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
592 __asm__ volatile ("sync");
593 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
594 /* make sure that we access a mirrored address */
595 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
596 __asm__ volatile ("sync");
597 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
598 /* SRAM size = 512 kByte */
599 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
601 __asm__ volatile ("sync");
602 puts ("SRAM: 512 kB\n");
605 puts ("!! possible error in SRAM detection\n");
607 puts ("SRAM: 1 MB\n");
609 /* restore origianl SRAM content */
611 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
612 __asm__ volatile ("sync");
615 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
617 * Check for Grafic Controller
620 /* save origianl FB content */
621 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
624 /* write test pattern to FB memory */
625 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
626 __asm__ volatile ("sync");
628 * Put a different pattern on the data lines: otherwise they may float
629 * long enough to read back what we wrote.
631 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
633 puts ("!! possible error in grafic controller detection\n");
635 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
636 /* no grafic controller at all, disable cs */
637 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
638 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
639 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
641 __asm__ volatile ("sync");
643 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
645 /* restore origianl FB content */
647 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
648 __asm__ volatile ("sync");
653 setenv("bootdelay", "0");
657 #endif /* !CONFIG_TQM5200S */
659 #if defined(CONFIG_CHARON)
660 charon_last_stage_init();
665 #ifdef CONFIG_VIDEO_SM501
668 #define DISPLAY_WIDTH 800
670 #define DISPLAY_WIDTH 640
672 #define DISPLAY_HEIGHT 480
674 #ifdef CONFIG_VIDEO_SM501_8BPP
675 #error CONFIG_VIDEO_SM501_8BPP not supported.
676 #endif /* CONFIG_VIDEO_SM501_8BPP */
678 #ifdef CONFIG_VIDEO_SM501_16BPP
679 #error CONFIG_VIDEO_SM501_16BPP not supported.
680 #endif /* CONFIG_VIDEO_SM501_16BPP */
681 #ifdef CONFIG_VIDEO_SM501_32BPP
682 static const SMI_REGS init_regs [] =
686 {0x00048, 0x00021807},
687 {0x0004C, 0x10090a01},
689 {0x00040, 0x00021807},
690 {0x00044, 0x10090a01},
692 {0x80200, 0x00010000},
694 {0x80208, 0x0A000A00},
695 {0x8020C, 0x02fa027f},
696 {0x80210, 0x004a028b},
697 {0x80214, 0x020c01df},
698 {0x80218, 0x000201e9},
699 {0x80200, 0x00013306},
700 #else /* panel + CRT */
703 {0x00048, 0x00021807},
704 {0x0004C, 0x301a0a01},
706 {0x00040, 0x00021807},
707 {0x00044, 0x091a0a01},
709 {0x80000, 0x0f013106},
710 {0x80004, 0xc428bb17},
711 {0x8000C, 0x00000000},
712 {0x80010, 0x0C800C80},
713 {0x80014, 0x03200000},
714 {0x80018, 0x01e00000},
715 {0x8001C, 0x00000000},
716 {0x80020, 0x01e00320},
717 {0x80024, 0x042a031f},
718 {0x80028, 0x0086034a},
719 {0x8002C, 0x020c01df},
720 {0x80030, 0x000201ea},
721 {0x80200, 0x00010000},
724 {0x00048, 0x00021807},
725 {0x0004C, 0x091a0a01},
727 {0x00040, 0x00021807},
728 {0x00044, 0x091a0a01},
730 {0x80000, 0x0f013106},
731 {0x80004, 0xc428bb17},
732 {0x8000C, 0x00000000},
733 {0x80010, 0x0a000a00},
734 {0x80014, 0x02800000},
735 {0x80018, 0x01e00000},
736 {0x8001C, 0x00000000},
737 {0x80020, 0x01e00280},
738 {0x80024, 0x02fa027f},
739 {0x80028, 0x004a028b},
740 {0x8002C, 0x020c01df},
741 {0x80030, 0x000201e9},
742 {0x80200, 0x00010000},
743 #endif /* #ifdef CONFIG_FO300 */
747 #endif /* CONFIG_VIDEO_SM501_32BPP */
749 #ifdef CONFIG_CONSOLE_EXTRA_INFO
751 * Return text to be printed besides the logo.
753 void video_get_info_str (int line_number, char *info)
755 if (line_number == 1) {
756 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
757 #if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
758 defined(CONFIG_STK52XX)
759 } else if (line_number == 2) {
760 #if defined (CONFIG_CHARON)
761 strcpy (info, " on a CHARON carrier board");
763 #if defined (CONFIG_STK52XX)
764 strcpy (info, " on a STK52xx carrier board");
766 #if defined (CONFIG_FO300)
767 strcpy (info, " on a FO300 carrier board");
778 * Returns SM501 register base address. First thing called in the
779 * driver. Checks if SM501 is physically present.
781 unsigned int board_video_init (void)
787 * Check for Grafic Controller
790 /* save origianl FB content */
791 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
794 /* write test pattern to FB memory */
795 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
796 __asm__ volatile ("sync");
798 * Put a different pattern on the data lines: otherwise they may float
799 * long enough to read back what we wrote.
801 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
803 puts ("!! possible error in grafic controller detection\n");
805 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
806 /* no grafic controller found */
810 ret = SM501_MMIO_BASE;
814 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
815 __asm__ volatile ("sync");
821 * Returns SM501 framebuffer address
823 unsigned int board_video_get_fb (void)
825 return SM501_FB_BASE;
829 * Called after initializing the SM501 and before clearing the screen.
831 void board_validate_screen (unsigned int base)
836 * Return a pointer to the initialization sequence.
838 const SMI_REGS *board_get_regs (void)
843 int board_get_width (void)
845 return DISPLAY_WIDTH;
848 int board_get_height (void)
850 return DISPLAY_HEIGHT;
853 #endif /* CONFIG_VIDEO_SM501 */
855 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
856 int ft_board_setup(void *blob, bd_t *bd)
858 ft_cpu_setup(blob, bd);
859 #if defined(CONFIG_VIDEO)
860 fdt_add_edid(blob, "smi,sm501", edid_buf);
865 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
867 #if defined(CONFIG_RESET_PHY_R)
872 /* init Micrel KSZ8993 PHY */
873 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
877 int board_eth_init(bd_t *bis)
879 cpu_eth_init(bis); /* Built in FEC comes first */
880 return pci_eth_init(bis);