3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/m8260_pci.h>
21 #define deb_printf(fmt,arg...) \
22 printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
24 #define deb_printf(fmt,arg...) \
28 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
29 unsigned long board_get_cpu_clk_f (void);
33 * I/O Port configuration table
35 * if conf is 1, then that port pin will be configured at boot time
36 * according to the five values podr/pdir/ppar/psor/pdat for that entry
39 const iop_conf_t iop_conf_tab[4][32] = {
41 /* Port A configuration */
42 { /* conf ppar psor pdir podr pdat */
43 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
44 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
45 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
46 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
47 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
48 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
49 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
50 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
51 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
52 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
53 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
54 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
55 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
56 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
57 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
58 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
59 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
60 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
61 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
62 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
63 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
64 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
65 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
66 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
67 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
68 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
69 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
70 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
71 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
72 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
73 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
74 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
77 /* Port B configuration */
78 { /* conf ppar psor pdir podr pdat */
79 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
80 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
81 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
82 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
83 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
84 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
85 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
86 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
87 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
88 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
89 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
90 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
91 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
92 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
93 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
94 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
95 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
96 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
97 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
98 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
99 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
100 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
101 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
102 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
103 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
104 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
105 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
106 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
107 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
108 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
109 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
110 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
114 { /* conf ppar psor pdir podr pdat */
115 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
116 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
117 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
118 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
119 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
120 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
121 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
122 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
123 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
124 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
125 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
126 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
127 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
128 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
129 /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */
130 /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/
131 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
132 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
133 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
134 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
135 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
136 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */
137 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */
138 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
139 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
140 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
141 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */
142 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */
143 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
144 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
145 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
146 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
150 { /* conf ppar psor pdir podr pdat */
151 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
152 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
153 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
154 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
155 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
156 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
157 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
158 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
159 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
160 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
161 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
162 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
163 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
164 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
165 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
166 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
167 #if defined(CONFIG_SYS_I2C_SOFT)
168 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
169 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
171 #if defined(CONFIG_HARD_I2C)
172 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
173 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
174 #else /* normal I/O port pins */
175 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
176 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
179 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
180 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
181 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
182 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
183 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
184 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
185 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
186 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
187 /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */
188 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
189 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
190 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
196 /* UPM pattern for slow init */
197 static const uint upmTableSlow[] =
199 /* Offset UPM Read Single RAM array entry */
200 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
201 /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
203 /* UPM Read Burst RAM array entry -> unused */
204 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
205 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
207 /* UPM Read Burst RAM array entry -> unused */
208 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
209 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
211 /* UPM Write Single RAM array entry */
212 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
213 /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
215 /* UPM Write Burst RAM array entry -> unused */
216 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
217 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
218 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
219 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
221 /* UPM Refresh Timer RAM array entry -> unused */
222 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
223 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
224 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
226 /* UPM Exception RAM array entry -> unused */
227 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
230 /* UPM pattern for fast init */
231 static const uint upmTableFast[] =
233 /* Offset UPM Read Single RAM array entry */
234 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
235 /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
237 /* UPM Read Burst RAM array entry -> unused */
238 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
239 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
241 /* UPM Read Burst RAM array entry -> unused */
242 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
243 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
245 /* UPM Write Single RAM array entry */
246 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
247 /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
249 /* UPM Write Burst RAM array entry -> unused */
250 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
251 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
252 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
253 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
255 /* UPM Refresh Timer RAM array entry -> unused */
256 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
257 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
258 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
260 /* UPM Exception RAM array entry -> unused */
261 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
265 /* ------------------------------------------------------------------------- */
267 /* Check Board Identity:
269 int checkboard (void)
271 char *p = (char *) HWIB_INFO_START_ADDR;
274 if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
277 puts ("No HWIB assuming TQM8272");
284 /* ------------------------------------------------------------------------- */
285 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
286 static int get_cas_latency (void)
288 /* get it from the option -ts in CIB */
292 char *p = (char *) CIB_INFO_START_ADDR;
294 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
295 if (*p < ' ' || *p > '~') { /* ASCII strings! */
299 if ((p[1] == 't') && (p[2] == 's')) {
310 static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
312 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
313 int clk = board_get_cpu_clk_f ();
314 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
315 int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
318 sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
323 sdmr |= (PSDMR_RFRC_66MHZ_60X | \
324 PSDMR_PRETOACT_66MHZ_60X | \
325 PSDMR_WRC_66MHZ_60X | \
326 PSDMR_BUFCMD_66MHZ_60X);
329 sdmr |= (PSDMR_RFRC_100MHZ_60X | \
330 PSDMR_PRETOACT_100MHZ_60X | \
331 PSDMR_WRC_100MHZ_60X | \
332 PSDMR_BUFCMD_100MHZ_60X);
339 sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
340 PSDMR_PRETOACT_66MHZ_SINGLE | \
341 PSDMR_WRC_66MHZ_SINGLE | \
342 PSDMR_BUFCMD_66MHZ_SINGLE);
345 sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
346 PSDMR_PRETOACT_100MHZ_SINGLE | \
347 PSDMR_WRC_100MHZ_SINGLE | \
348 PSDMR_BUFCMD_100MHZ_SINGLE);
351 sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
352 PSDMR_PRETOACT_133MHZ_SINGLE | \
353 PSDMR_WRC_133MHZ_SINGLE | \
354 PSDMR_BUFCMD_133MHZ_SINGLE);
358 cas = get_cas_latency();
359 sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
361 sdmr |= ((cas - 1) << 6);
368 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
370 * This routine performs standard 8260 initialization sequence
371 * and calculates the available memory size. It may be called
372 * several times to try different SDRAM configurations on both
373 * 60x and local buses.
375 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
376 ulong orx, volatile uchar * base, int col)
378 volatile uchar c = 0xff;
379 volatile uint *sdmr_ptr;
380 volatile uint *orx_ptr;
384 /* We must be able to test a location outsize the maximum legal size
385 * to find out THAT we are outside; but this address still has to be
386 * mapped by the controller. That means, that the initial mapping has
387 * to be (at least) twice as large as the maximum expected size.
389 maxsize = (1 + (~orx | 0x7fff)) / 2;
391 /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
392 * we are configuring CS1 if base != 0
394 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
395 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
398 sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
400 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
402 * "At system reset, initialization software must set up the
403 * programmable parameters in the memory controller banks registers
404 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
405 * system software should execute the following initialization sequence
406 * for each SDRAM device.
408 * 1. Issue a PRECHARGE-ALL-BANKS command
409 * 2. Issue eight CBR REFRESH commands
410 * 3. Issue a MODE-SET command to initialize the mode register
412 * The initial commands are executed by setting P/LSDMR[OP] and
413 * accessing the SDRAM with a single-byte transaction."
415 * The appropriate BRx/ORx registers have already been set when we
416 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
419 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
422 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
423 for (i = 0; i < 8; i++)
426 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
427 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
429 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
432 size = get_ram_size((long *)base, maxsize);
433 *orx_ptr = orx | ~(size - 1);
438 phys_size_t initdram (int board_type)
440 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
441 volatile memctl8260_t *memctl = &immap->im_memctl;
443 #ifndef CONFIG_SYS_RAMBOOT
448 psize = 16 * 1024 * 1024;
450 memctl->memc_psrt = CONFIG_SYS_PSRT;
451 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
453 #ifndef CONFIG_SYS_RAMBOOT
456 size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
457 (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
458 size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
459 (uchar *) CONFIG_SYS_SDRAM_BASE, 9);
463 printf ("(60x:9COL - %ld MB, ", psize >> 20);
465 psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
466 (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
467 printf ("(60x:8COL - %ld MB, ", psize >> 20);
470 #endif /* CONFIG_SYS_RAMBOOT */
478 static inline int scanChar (char *p, int len, unsigned long *number)
484 if ((*p >= '0') && (*p <= '9')) {
489 if (*p == '-') return akt;
497 static int dump_hwib(void)
499 HWIB_INFO *hw = &hwinf;
501 int i = getenv_f("serial#", buf, sizeof(buf));
502 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
508 printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
509 printf ("serial : %s\n", buf);
510 printf ("ethaddr: %s\n", hw->ethaddr);
511 printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr);
512 printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs);
513 printf ("CPU : %lu\n", hw->cpunr);
514 printf ("CAN : %d\n", hw->can);
515 if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
516 else printf ("No EEprom\n");
518 printf ("NAND : %x\n", hw->nand);
519 printf ("NAND CS: %d\n", hw->nand_cs);
520 } else { printf ("No NAND\n");}
521 printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
522 printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
523 "60x" : "Single PQII"));
524 printf ("Option : %lx\n", hw->option);
525 printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
526 printf ("CPM Clk: %d\n", hw->cpmcl);
527 printf ("CPU Clk: %d\n", hw->cpucl);
528 printf ("Bus Clk: %d\n", hw->buscl);
529 if (hw->busclk_real_ok) {
530 printf (" real Clk: %d\n", hw->busclk_real);
532 printf ("CAS : %d\n", get_cas_latency());
534 printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
539 static inline int search_real_busclk (int *clk)
541 int part = 0, pos = 0;
542 char *p = (char *) CIB_INFO_START_ADDR;
545 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
546 if (*p < ' ' || *p > '~') { /* ASCII strings! */
588 int analyse_hwib (void)
590 char *p = (char *) HWIB_INFO_START_ADDR;
592 int part = 1, i = 0, pos = 0;
593 HWIB_INFO *hw = &hwinf;
595 deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
597 if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
598 deb_printf("No HWIB\n");
602 if (scanChar (p, 4, &hw->cpunr) < 0) {
603 deb_printf("No CPU\n");
608 hw->flash = 0x200000 << (*p - 'A');
610 hw->flash_nr = *p - '0';
613 hw->ram = 0x2000000 << (*p - 'A');
620 if (*p == 'A') hw->can = 1;
621 if (*p == 'B') hw->can = 2;
623 p +=1; /* connector */
625 hw->eeprom = 0x1000 << (*p - 'A');
629 if ((*p < '0') || (*p > '9')) {
630 /* NAND before z-option */
631 hw->nand = 0x8000000 << (*p - 'A');
633 hw->nand_cs = *p - '0';
637 anz = scanChar (p, 4, &hw->option);
639 deb_printf("No option\n");
642 if (hw->option & 0x8) hw->Bus = 1;
645 deb_printf("No -\n");
655 case 'M': hw->cpucl = 266666666;
657 case 'P': hw->cpucl = 300000000;
659 case 'T': hw->cpucl = 400000000;
662 deb_printf("No CPU Clk: %c\n", *p);
668 case 'I': hw->cpmcl = 200000000;
670 case 'M': hw->cpmcl = 300000000;
673 deb_printf("No CPM Clk\n");
679 case 'B': hw->buscl = 66666666;
681 case 'E': hw->buscl = 100000000;
683 case 'F': hw->buscl = 133333333;
686 deb_printf("No BUS Clk\n");
693 /* search MAC Address */
694 while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) {
695 if (*p < ' ' || *p > '~') { /* ASCII strings! */
705 case 3: /* Copy MAC address */
711 hw->ethaddr[i++] = *p;
713 hw->ethaddr[i++] = ':';
720 hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
724 #if defined(CONFIG_GET_CPU_STR_F)
725 /* !! This routine runs from Flash */
726 char get_cpu_str_f (char *buf)
728 char *p = (char *) HWIB_INFO_START_ADDR;
734 if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
750 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
751 /* !! This routine runs from Flash */
752 unsigned long board_get_cpu_clk_f (void)
754 char *p = (char *) HWIB_INFO_START_ADDR;
757 if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
758 if (search_real_busclk (&i))
761 return CONFIG_8260_CLKIN;
765 #if CONFIG_BOARD_EARLY_INIT_R
767 static int can_test (unsigned long off)
769 volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
771 *(base + 0x17) = 'T';
772 *(base + 0x18) = 'Q';
773 *(base + 0x19) = 'M';
774 if ((*(base + 0x17) != 'T') ||
775 (*(base + 0x18) != 'Q') ||
776 (*(base + 0x19) != 'M')) {
782 static int can_config_one (unsigned long off)
784 volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
785 volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02);
786 volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f);
800 static int can_config (void)
804 if (hwinf.can == 2) {
805 can_config_one (0x100);
807 /* make Test if they really there */
809 ret += can_test (0x100);
813 static int init_can (void)
815 volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
816 volatile memctl8260_t *memctl = &immr->im_memctl;
819 if ((hwinf.OK) && (hwinf.can)) {
820 memctl->memc_or4 = CONFIG_SYS_CAN_OR;
821 memctl->memc_br4 = CONFIG_SYS_CAN_BR;
823 upmconfig (UPMC, (uint *) upmTableFast,
824 sizeof (upmTableFast) / sizeof (uint));
825 memctl->memc_mcmr = (MxMR_DSx_3_CYCL |
831 count = can_config ();
832 printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE);
833 if (hwinf.can != count) printf("!!! difference to HWIB\n");
835 printf ("CAN: No\n");
840 int board_early_init_r(void)
848 int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
855 hwib, 1, 1, do_hwib_dump,
860 #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
861 static int get_flash_timing (void)
863 /* get it from the option -tf in CIB */
864 /* default is 0x00000c84 */
865 int ret = 0x00000c84;
868 char *p = (char *) CIB_INFO_START_ADDR;
870 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
871 if (*p < ' ' || *p > '~') { /* ASCII strings! */
875 if ((p[1] == 't') && (p[2] == 'f')) {
879 if ((*p >= '0') && (*p <= '9')) {
884 } else if ((*p >= 'A') && (*p <= 'F')) {
890 if (nr < 8) return 0x00000c84;
902 /* Update the Flash_Size and the Flash Timing */
903 int update_flash_size (int flash_size)
905 volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
906 volatile memctl8260_t *memctl = &immr->im_memctl;
910 /* I must use reg, otherwise the board hang */
911 reg = memctl->memc_or0;
913 reg |= MEG_TO_AM(flash_size >> 20);
914 tim = get_flash_timing ();
916 reg |= (tim & 0xfff);
917 memctl->memc_or0 = reg;
923 struct pci_controller hose;
925 int board_early_init_f (void)
927 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
929 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
933 extern void pci_mpc8250_init(struct pci_controller *);
935 void pci_init_board(void)
937 pci_mpc8250_init(&hose);
941 int board_eth_init(bd_t *bis)
943 return pci_eth_init(bis);