3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/m8260_pci.h>
36 #define deb_printf(fmt,arg...) \
37 printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
39 #define deb_printf(fmt,arg...) \
43 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
44 unsigned long board_get_cpu_clk_f (void);
48 * I/O Port configuration table
50 * if conf is 1, then that port pin will be configured at boot time
51 * according to the five values podr/pdir/ppar/psor/pdat for that entry
54 const iop_conf_t iop_conf_tab[4][32] = {
56 /* Port A configuration */
57 { /* conf ppar psor pdir podr pdat */
58 /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
59 /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
60 /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
61 /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
62 /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
63 /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
64 /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
65 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
66 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
67 /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
68 /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
69 /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
70 /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
71 /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
72 /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
73 /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
74 /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
75 /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
76 /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
77 /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
78 /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
79 /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
80 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
81 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
82 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
83 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
84 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
85 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
86 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
87 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
88 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
89 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
92 /* Port B configuration */
93 { /* conf ppar psor pdir podr pdat */
94 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
95 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
96 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
97 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
98 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
99 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
100 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
101 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
102 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
103 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
104 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
105 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
106 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
107 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
108 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
109 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
110 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
111 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
112 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
113 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
114 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
115 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
116 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
117 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
118 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
119 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
120 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
121 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
122 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
124 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
125 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
129 { /* conf ppar psor pdir podr pdat */
130 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
131 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
132 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
133 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
134 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
135 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
136 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
137 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
138 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
139 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
140 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
141 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
142 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
143 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
144 /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */
145 /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/
146 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
147 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
148 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
149 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
150 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
151 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */
152 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */
153 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
154 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
155 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
156 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */
157 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */
158 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
159 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
160 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
161 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
165 { /* conf ppar psor pdir podr pdat */
166 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
167 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
168 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
169 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
170 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
171 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
172 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
173 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
174 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
175 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
176 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
177 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
178 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
179 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
180 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
181 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
182 #if defined(CONFIG_SOFT_I2C)
183 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
184 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
186 #if defined(CONFIG_HARD_I2C)
187 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
188 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
189 #else /* normal I/O port pins */
190 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
191 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
194 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
195 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
196 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
197 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
198 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
199 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
200 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
201 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
202 /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */
203 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
204 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
205 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
206 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
207 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
211 #define _NOT_USED_ 0xFFFFFFFF
213 /* UPM pattern for bus clock = 66.7 MHz */
214 static const uint upmTable67[] =
216 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
217 /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
218 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
220 /* UPM Read Burst RAM array entry -> unused */
221 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
222 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
224 /* UPM Read Burst RAM array entry -> unused */
225 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
226 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
228 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
229 /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
230 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
232 /* UPM Write Burst RAM array entry -> unused */
233 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
234 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
235 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
236 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
238 /* UPM Refresh Timer RAM array entry -> unused */
239 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
240 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
241 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
243 /* UPM Exception RAM array entry -> unsused */
244 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
247 /* UPM pattern for bus clock = 100 MHz */
248 static const uint upmTable100[] =
250 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
251 /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
252 /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
254 /* UPM Read Burst RAM array entry -> unused */
255 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
256 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
258 /* UPM Read Burst RAM array entry -> unused */
259 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
260 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
262 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
263 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
264 /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
266 /* UPM Write Burst RAM array entry -> unused */
267 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
268 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
269 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
270 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
272 /* UPM Refresh Timer RAM array entry -> unused */
273 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
274 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
275 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
277 /* UPM Exception RAM array entry -> unsused */
278 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
281 /* UPM pattern for bus clock = 133.3 MHz */
282 static const uint upmTable133[] =
284 /* Offset UPM Read Single RAM array entry -> NAND Read Data */
285 /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
286 /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
288 /* UPM Read Burst RAM array entry -> unused */
289 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
290 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
292 /* UPM Read Burst RAM array entry -> unused */
293 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
294 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
296 /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
297 /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
298 /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
300 /* UPM Write Burst RAM array entry -> unused */
301 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
302 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
303 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
304 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
306 /* UPM Refresh Timer RAM array entry -> unused */
307 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
308 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
309 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
311 /* UPM Exception RAM array entry -> unsused */
312 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
315 static int chipsel = 0;
317 /* UPM pattern for slow init */
318 static const uint upmTableSlow[] =
320 /* Offset UPM Read Single RAM array entry */
321 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
322 /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
324 /* UPM Read Burst RAM array entry -> unused */
325 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
326 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
328 /* UPM Read Burst RAM array entry -> unused */
329 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
330 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
332 /* UPM Write Single RAM array entry */
333 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
334 /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
336 /* UPM Write Burst RAM array entry -> unused */
337 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
338 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
339 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
340 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
342 /* UPM Refresh Timer RAM array entry -> unused */
343 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
344 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
345 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
347 /* UPM Exception RAM array entry -> unused */
348 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
351 /* UPM pattern for fast init */
352 static const uint upmTableFast[] =
354 /* Offset UPM Read Single RAM array entry */
355 /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
356 /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
358 /* UPM Read Burst RAM array entry -> unused */
359 /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
360 /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
362 /* UPM Read Burst RAM array entry -> unused */
363 /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
364 /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
366 /* UPM Write Single RAM array entry */
367 /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
368 /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
370 /* UPM Write Burst RAM array entry -> unused */
371 /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
372 /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
373 /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
374 /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
376 /* UPM Refresh Timer RAM array entry -> unused */
377 /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
378 /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
379 /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
381 /* UPM Exception RAM array entry -> unused */
382 /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
386 /* ------------------------------------------------------------------------- */
388 /* Check Board Identity:
390 int checkboard (void)
392 char *p = (char *) HWIB_INFO_START_ADDR;
395 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
398 puts ("No HWIB assuming TQM8272");
405 /* ------------------------------------------------------------------------- */
406 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
407 static int get_cas_latency (void)
409 /* get it from the option -ts in CIB */
413 char *p = (char *) CIB_INFO_START_ADDR;
415 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
416 if (*p < ' ' || *p > '~') { /* ASCII strings! */
420 if ((p[1] == 't') && (p[2] == 's')) {
431 static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
433 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
434 int clk = board_get_cpu_clk_f ();
435 volatile immap_t *immr = (immap_t *)CFG_IMMR;
436 int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
439 sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
444 sdmr |= (PSDMR_RFRC_66MHZ_60X | \
445 PSDMR_PRETOACT_66MHZ_60X | \
446 PSDMR_WRC_66MHZ_60X | \
447 PSDMR_BUFCMD_66MHZ_60X);
450 sdmr |= (PSDMR_RFRC_100MHZ_60X | \
451 PSDMR_PRETOACT_100MHZ_60X | \
452 PSDMR_WRC_100MHZ_60X | \
453 PSDMR_BUFCMD_100MHZ_60X);
460 sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
461 PSDMR_PRETOACT_66MHZ_SINGLE | \
462 PSDMR_WRC_66MHZ_SINGLE | \
463 PSDMR_BUFCMD_66MHZ_SINGLE);
466 sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
467 PSDMR_PRETOACT_100MHZ_SINGLE | \
468 PSDMR_WRC_100MHZ_SINGLE | \
469 PSDMR_BUFCMD_100MHZ_SINGLE);
472 sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
473 PSDMR_PRETOACT_133MHZ_SINGLE | \
474 PSDMR_WRC_133MHZ_SINGLE | \
475 PSDMR_BUFCMD_133MHZ_SINGLE);
479 cas = get_cas_latency();
480 sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
482 sdmr |= ((cas - 1) << 6);
489 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
491 * This routine performs standard 8260 initialization sequence
492 * and calculates the available memory size. It may be called
493 * several times to try different SDRAM configurations on both
494 * 60x and local buses.
496 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
497 ulong orx, volatile uchar * base, int col)
499 volatile uchar c = 0xff;
500 volatile uint *sdmr_ptr;
501 volatile uint *orx_ptr;
505 /* We must be able to test a location outsize the maximum legal size
506 * to find out THAT we are outside; but this address still has to be
507 * mapped by the controller. That means, that the initial mapping has
508 * to be (at least) twice as large as the maximum expected size.
510 maxsize = (1 + (~orx | 0x7fff)) / 2;
512 /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
513 * we are configuring CS1 if base != 0
515 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
516 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
519 sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
521 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
523 * "At system reset, initialization software must set up the
524 * programmable parameters in the memory controller banks registers
525 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
526 * system software should execute the following initialization sequence
527 * for each SDRAM device.
529 * 1. Issue a PRECHARGE-ALL-BANKS command
530 * 2. Issue eight CBR REFRESH commands
531 * 3. Issue a MODE-SET command to initialize the mode register
533 * The initial commands are executed by setting P/LSDMR[OP] and
534 * accessing the SDRAM with a single-byte transaction."
536 * The appropriate BRx/ORx registers have already been set when we
537 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
540 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
543 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
544 for (i = 0; i < 8; i++)
547 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
548 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
550 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
553 size = get_ram_size((long *)base, maxsize);
554 *orx_ptr = orx | ~(size - 1);
559 phys_size_t initdram (int board_type)
561 volatile immap_t *immap = (immap_t *) CFG_IMMR;
562 volatile memctl8260_t *memctl = &immap->im_memctl;
569 psize = 16 * 1024 * 1024;
572 memctl->memc_psrt = CFG_PSRT;
573 memctl->memc_mptpr = CFG_MPTPR;
578 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
579 (uchar *) CFG_SDRAM_BASE, 8);
580 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
581 (uchar *) CFG_SDRAM_BASE, 9);
585 printf ("(60x:9COL - %ld MB, ", psize >> 20);
587 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
588 (uchar *) CFG_SDRAM_BASE, 8);
589 printf ("(60x:8COL - %ld MB, ", psize >> 20);
592 #endif /* CFG_RAMBOOT */
600 static inline int scanChar (char *p, int len, unsigned long *number)
606 if ((*p >= '0') && (*p <= '9')) {
611 if (*p == '-') return akt;
630 unsigned long option;
638 unsigned char ethaddr[20];
641 HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
644 static int dump_hwib(void)
646 HWIB_INFO *hw = &hwinf;
647 volatile immap_t *immr = (immap_t *)CFG_IMMR;
648 char *s = getenv("serial#");
651 printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
652 printf ("serial : %s\n", s);
653 printf ("ethaddr: %s\n", hw->ethaddr);
654 printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr);
655 printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs);
656 printf ("CPU : %lu\n", hw->cpunr);
657 printf ("CAN : %d\n", hw->can);
658 if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
659 else printf ("No EEprom\n");
661 printf ("NAND : %x\n", hw->nand);
662 printf ("NAND CS: %d\n", hw->nand_cs);
663 } else { printf ("No NAND\n");}
664 printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
665 printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
666 "60x" : "Single PQII"));
667 printf ("Option : %lx\n", hw->option);
668 printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
669 printf ("CPM Clk: %d\n", hw->cpmcl);
670 printf ("CPU Clk: %d\n", hw->cpucl);
671 printf ("Bus Clk: %d\n", hw->buscl);
672 if (hw->busclk_real_ok) {
673 printf (" real Clk: %d\n", hw->busclk_real);
675 printf ("CAS : %d\n", get_cas_latency());
677 printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
682 static inline int search_real_busclk (int *clk)
684 int part = 0, pos = 0;
685 char *p = (char *) CIB_INFO_START_ADDR;
688 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
689 if (*p < ' ' || *p > '~') { /* ASCII strings! */
731 int analyse_hwib (void)
733 char *p = (char *) HWIB_INFO_START_ADDR;
735 int part = 1, i = 0, pos = 0;
736 HWIB_INFO *hw = &hwinf;
738 deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
740 if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) {
741 deb_printf("No HWIB\n");
745 if (scanChar (p, 4, &hw->cpunr) < 0) {
746 deb_printf("No CPU\n");
751 hw->flash = 0x200000 << (*p - 'A');
753 hw->flash_nr = *p - '0';
756 hw->ram = 0x2000000 << (*p - 'A');
763 if (*p == 'A') hw->can = 1;
764 if (*p == 'B') hw->can = 2;
766 p +=1; /* connector */
768 hw->eeprom = 0x1000 << (*p - 'A');
772 if ((*p < '0') || (*p > '9')) {
773 /* NAND before z-option */
774 hw->nand = 0x8000000 << (*p - 'A');
776 hw->nand_cs = *p - '0';
780 anz = scanChar (p, 4, &hw->option);
782 deb_printf("No option\n");
785 if (hw->option & 0x8) hw->Bus = 1;
788 deb_printf("No -\n");
798 case 'M': hw->cpucl = 266666666;
800 case 'P': hw->cpucl = 300000000;
802 case 'T': hw->cpucl = 400000000;
805 deb_printf("No CPU Clk: %c\n", *p);
811 case 'I': hw->cpmcl = 200000000;
813 case 'M': hw->cpmcl = 300000000;
816 deb_printf("No CPM Clk\n");
822 case 'B': hw->buscl = 66666666;
824 case 'E': hw->buscl = 100000000;
826 case 'F': hw->buscl = 133333333;
829 deb_printf("No BUS Clk\n");
836 /* search MAC Address */
837 while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) {
838 if (*p < ' ' || *p > '~') { /* ASCII strings! */
848 case 3: /* Copy MAC address */
854 hw->ethaddr[i++] = *p;
856 hw->ethaddr[i++] = ':';
863 hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
867 #if defined(CONFIG_GET_CPU_STR_F)
868 /* !! This routine runs from Flash */
869 char get_cpu_str_f (char *buf)
871 char *p = (char *) HWIB_INFO_START_ADDR;
877 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
893 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
894 /* !! This routine runs from Flash */
895 unsigned long board_get_cpu_clk_f (void)
897 char *p = (char *) HWIB_INFO_START_ADDR;
900 if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
901 if (search_real_busclk (&i))
904 return CONFIG_8260_CLKIN;
908 #if CONFIG_BOARD_EARLY_INIT_R
910 static int can_test (unsigned long off)
912 volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off);
914 *(base + 0x17) = 'T';
915 *(base + 0x18) = 'Q';
916 *(base + 0x19) = 'M';
917 if ((*(base + 0x17) != 'T') ||
918 (*(base + 0x18) != 'Q') ||
919 (*(base + 0x19) != 'M')) {
925 static int can_config_one (unsigned long off)
927 volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off);
928 volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
929 volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
943 static int can_config (void)
947 if (hwinf.can == 2) {
948 can_config_one (0x100);
950 /* make Test if they really there */
952 ret += can_test (0x100);
956 static int init_can (void)
958 volatile immap_t * immr = (immap_t *)CFG_IMMR;
959 volatile memctl8260_t *memctl = &immr->im_memctl;
962 if ((hwinf.OK) && (hwinf.can)) {
963 memctl->memc_or4 = CFG_CAN_OR;
964 memctl->memc_br4 = CFG_CAN_BR;
966 upmconfig (UPMC, (uint *) upmTableFast,
967 sizeof (upmTableFast) / sizeof (uint));
968 memctl->memc_mcmr = (MxMR_DSx_3_CYCL |
974 count = can_config ();
975 printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE);
976 if (hwinf.can != count) printf("!!! difference to HWIB\n");
978 printf ("CAN: No\n");
983 int board_early_init_r(void)
991 int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
998 hwib, 1, 1, do_hwib_dump,
999 "hwib - dump HWIB'\n",
1003 #ifdef CFG_UPDATE_FLASH_SIZE
1004 static int get_flash_timing (void)
1006 /* get it from the option -tf in CIB */
1007 /* default is 0x00000c84 */
1008 int ret = 0x00000c84;
1011 char *p = (char *) CIB_INFO_START_ADDR;
1013 while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
1014 if (*p < ' ' || *p > '~') { /* ASCII strings! */
1018 if ((p[1] == 't') && (p[2] == 'f')) {
1022 if ((*p >= '0') && (*p <= '9')) {
1027 } else if ((*p >= 'A') && (*p <= 'F')) {
1033 if (nr < 8) return 0x00000c84;
1045 /* Update the Flash_Size and the Flash Timing */
1046 int update_flash_size (int flash_size)
1048 volatile immap_t * immr = (immap_t *)CFG_IMMR;
1049 volatile memctl8260_t *memctl = &immr->im_memctl;
1053 /* I must use reg, otherwise the board hang */
1054 reg = memctl->memc_or0;
1055 reg &= ~ORxU_AM_MSK;
1056 reg |= MEG_TO_AM(flash_size >> 20);
1057 tim = get_flash_timing ();
1059 reg |= (tim & 0xfff);
1060 memctl->memc_or0 = reg;
1065 #if defined(CONFIG_CMD_NAND)
1068 #include <linux/mtd/mtd.h>
1070 static u8 hwctl = 0;
1072 static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
1074 struct nand_chip *this = mtd->priv;
1076 if (ctrl & NAND_CTRL_CHANGE) {
1077 if ( ctrl & NAND_CLE )
1081 if ( ctrl & NAND_ALE )
1086 if (cmd != NAND_CMD_NONE)
1087 writeb(cmd, this->IO_ADDR_W);
1090 static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
1092 struct nand_chip *this = mtdinfo->priv;
1093 ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1096 WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
1097 } else if (hwctl & 0x2) {
1098 WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
1100 WRITE_NAND(byte, base);
1104 static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
1106 struct nand_chip *this = mtdinfo->priv;
1107 ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1109 return READ_NAND(base);
1112 static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
1114 /* constant delay (see also tR in the datasheet) */
1119 #ifndef CONFIG_NAND_SPL
1120 static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
1122 struct nand_chip *this = mtdinfo->priv;
1123 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1126 for (i = 0; i< len; i++)
1130 static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
1132 struct nand_chip *this = mtdinfo->priv;
1133 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1136 for (i = 0; i< len; i++)
1140 static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
1142 struct nand_chip *this = mtdinfo->priv;
1143 unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
1146 for (i = 0; i < len; i++)
1147 if (buf[i] != *base)
1151 #endif /* #ifndef CONFIG_NAND_SPL */
1153 void board_nand_select_device(struct nand_chip *nand, int chip)
1158 int board_nand_init(struct nand_chip *nand)
1160 static int UpmInit = 0;
1161 volatile immap_t * immr = (immap_t *)CFG_IMMR;
1162 volatile memctl8260_t *memctl = &immr->im_memctl;
1164 if (hwinf.nand == 0) return -1;
1168 switch (hwinf.busclk_real) {
1170 upmconfig (UPMB, (uint *) upmTable100,
1171 sizeof (upmTable100) / sizeof (uint));
1174 upmconfig (UPMB, (uint *) upmTable133,
1175 sizeof (upmTable133) / sizeof (uint));
1178 upmconfig (UPMB, (uint *) upmTable67,
1179 sizeof (upmTable67) / sizeof (uint));
1185 /* Setup the memctrl */
1186 memctl->memc_or3 = CFG_NAND_OR;
1187 memctl->memc_br3 = CFG_NAND_BR;
1188 memctl->memc_mbmr = (MxMR_OP_NORM);
1190 nand->ecc.mode = NAND_ECC_SOFT;
1192 nand->cmd_ctrl = upmnand_hwcontrol;
1193 nand->read_byte = upmnand_read_byte;
1194 nand->write_byte = upmnand_write_byte;
1195 nand->dev_ready = tqm8272_dev_ready;
1197 #ifndef CONFIG_NAND_SPL
1198 nand->write_buf = tqm8272_write_buf;
1199 nand->read_buf = tqm8272_read_buf;
1200 nand->verify_buf = tqm8272_verify_buf;
1204 * Select required NAND chip
1206 board_nand_select_device(nand, 0);
1213 struct pci_controller hose;
1215 int board_early_init_f (void)
1217 volatile immap_t *immap = (immap_t *) CFG_IMMR;
1219 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
1223 extern void pci_mpc8250_init(struct pci_controller *);
1225 void pci_init_board(void)
1227 pci_mpc8250_init(&hose);
1231 int board_eth_init(bd_t *bis)
1233 return pci_eth_init(bis);