2 * Copyright 2008 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
31 SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
32 MAS3_SX | MAS3_SW | MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
34 SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
35 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
36 MAS3_SX | MAS3_SW | MAS3_SR, 0,
37 0, 0, BOOKE_PAGESZ_4K, 0),
38 SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
39 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
40 MAS3_SX | MAS3_SW | MAS3_SR, 0,
41 0, 0, BOOKE_PAGESZ_4K, 0),
42 SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
43 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
44 MAS3_SX | MAS3_SW | MAS3_SR, 0,
45 0, 0, BOOKE_PAGESZ_4K, 0),
47 #ifndef CONFIG_TQM_BIGFLASH
49 * TLB 0, 1: 128M Non-cacheable, guarded
50 * 0xf8000000 128M FLASH
51 * Out of reset this entry is only 4K.
53 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
54 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
55 0, 1, BOOKE_PAGESZ_64M, 1),
56 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
57 CONFIG_SYS_FLASH_BASE + 0x4000000,
58 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
59 0, 0, BOOKE_PAGESZ_64M, 1),
62 * TLB 2: 256M Non-cacheable, guarded
63 * 0x80000000 256M PCI1 MEM First half
65 SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
66 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
67 0, 2, BOOKE_PAGESZ_256M, 1),
70 * TLB 3: 256M Non-cacheable, guarded
71 * 0x90000000 256M PCI1 MEM Second half
73 SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
74 CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
75 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
76 0, 3, BOOKE_PAGESZ_256M, 1),
80 * TLB 4: 256M Non-cacheable, guarded
81 * 0xc0000000 256M PCI express MEM First half
83 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
84 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
85 0, 4, BOOKE_PAGESZ_256M, 1),
88 * TLB 5: 256M Non-cacheable, guarded
89 * 0xd0000000 256M PCI express MEM Second half
91 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
92 CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
93 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
94 0, 5, BOOKE_PAGESZ_256M, 1),
95 #else /* !CONFIG_PCIE */
97 * TLB 4: 256M Non-cacheable, guarded
98 * 0xc0000000 256M Rapid IO MEM First half
100 SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
101 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
102 0, 4, BOOKE_PAGESZ_256M, 1),
105 * TLB 5: 256M Non-cacheable, guarded
106 * 0xd0000000 256M Rapid IO MEM Second half
108 SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
109 CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
110 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
111 0, 5, BOOKE_PAGESZ_256M, 1),
112 #endif /* CONFIG_PCIE */
115 * TLB 6: 64M Non-cacheable, guarded
116 * 0xe0000000 1M CCSRBAR
117 * 0xe2000000 16M PCI1 IO
118 * 0xe3000000 16M CAN and NAND Flash
120 SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
121 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
122 0, 6, BOOKE_PAGESZ_64M, 1),
124 #if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
126 * TLB 7+8: 2G DDR, cache enabled
127 * 0x00000000 2G DDR System memory
128 * Without SPD EEPROM configured DDR, this must be setup manually.
130 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
131 MAS3_SX | MAS3_SW | MAS3_SR, 0,
132 0, 7, BOOKE_PAGESZ_1G, 1),
134 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
135 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
136 MAS3_SX | MAS3_SW | MAS3_SR, 0,
137 0, 8, BOOKE_PAGESZ_1G, 1),
140 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
141 * 0x00000000 512M DDR System memory
142 * Without SPD EEPROM configured DDR, this must be setup manually.
144 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
145 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
146 0, 7, BOOKE_PAGESZ_256M, 1),
148 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
149 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
150 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
151 0, 8, BOOKE_PAGESZ_256M, 1),
155 * TLB 9: 16M Non-cacheable, guarded
156 * 0xef000000 16M PCI express IO
158 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
159 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
160 0, 9, BOOKE_PAGESZ_16M, 1),
161 #endif /* CONFIG_PCIE */
163 #else /* CONFIG_TQM_BIGFLASH */
166 * TLB 0,1,2,3: 1G Non-cacheable, guarded
167 * 0xc0000000 1G FLASH
168 * Out of reset this entry is only 4K.
170 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
171 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
172 0, 3, BOOKE_PAGESZ_256M, 1),
173 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
174 CONFIG_SYS_FLASH_BASE + 0x10000000,
175 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
176 0, 2, BOOKE_PAGESZ_256M, 1),
177 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
178 CONFIG_SYS_FLASH_BASE + 0x20000000,
179 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
180 0, 1, BOOKE_PAGESZ_256M, 1),
181 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
182 CONFIG_SYS_FLASH_BASE + 0x30000000,
183 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
184 0, 0, BOOKE_PAGESZ_256M, 1),
187 * TLB 4: 256M Non-cacheable, guarded
188 * 0x80000000 256M PCI1 MEM First half
190 SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
191 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
192 0, 4, BOOKE_PAGESZ_256M, 1),
195 * TLB 5: 256M Non-cacheable, guarded
196 * 0x90000000 256M PCI1 MEM Second half
198 SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
199 CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
200 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
201 0, 5, BOOKE_PAGESZ_256M, 1),
205 * TLB 6: 256M Non-cacheable, guarded
206 * 0xc0000000 256M PCI express MEM First half
208 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
209 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
210 0, 6, BOOKE_PAGESZ_256M, 1),
211 #else /* !CONFIG_PCIE */
213 * TLB 6: 256M Non-cacheable, guarded
214 * 0xb0000000 256M Rapid IO MEM First half
216 SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
217 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
218 0, 6, BOOKE_PAGESZ_256M, 1),
220 #endif /* CONFIG_PCIE */
223 * TLB 7: 64M Non-cacheable, guarded
224 * 0xa0000000 1M CCSRBAR
225 * 0xa2000000 16M PCI1 IO
226 * 0xa3000000 16M CAN and NAND Flash
228 SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
229 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
230 0, 7, BOOKE_PAGESZ_64M, 1),
233 * TLB 8+9: 512M DDR, cache disabled (needed for memory test)
234 * 0x00000000 512M DDR System memory
235 * Without SPD EEPROM configured DDR, this must be setup manually.
236 * Make sure the TLB count at the top of this table is correct.
237 * Likely it needs to be increased by two for these entries.
239 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
240 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
241 0, 8, BOOKE_PAGESZ_256M, 1),
243 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
244 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
245 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
246 0, 9, BOOKE_PAGESZ_256M, 1),
250 * TLB 10: 16M Non-cacheable, guarded
251 * 0xaf000000 16M PCI express IO
253 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
254 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
255 0, 10, BOOKE_PAGESZ_16M, 1),
256 #endif /* CONFIG_PCIE */
258 #endif /* CONFIG_TQM_BIGFLASH */
261 int num_tlb_entries = ARRAY_SIZE (tlb_table);