3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Copyright 2004 Freescale Semiconductor.
6 * (C) Copyright 2002,2003, Motorola Inc.
7 * Xianghua Xiao, (X.Xiao@motorola.com)
9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/processor.h>
33 #include <asm/immap_85xx.h>
38 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 extern flash_info_t flash_info[]; /* FLASH chips info */
44 void local_bus_init (void);
45 ulong flash_get_size (ulong base, int banknum);
48 void ps2mult_early_init (void);
53 * I/O Port configuration table
55 * if conf is 1, then that port pin will be configured at boot time
56 * according to the five values podr/pdir/ppar/psor/pdat for that entry
59 const iop_conf_t iop_conf_tab[4][32] = {
61 /* Port A: conf, ppar, psor, pdir, podr, pdat */
63 {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
64 {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
65 {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
66 {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
67 {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
68 {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
69 {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
70 {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
71 {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
72 {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
73 {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
74 {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
75 {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
76 {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
77 {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
78 {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
79 {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
80 {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
81 {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
82 {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
83 {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
84 {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
85 {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
86 {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
87 {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
88 {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
89 {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
90 {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
91 {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
92 {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
93 {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
94 {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
97 /* Port B: conf, ppar, psor, pdir, podr, pdat */
99 {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
100 {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
101 {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
102 {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
103 {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
104 {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
105 {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
106 {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
107 {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
108 {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
109 {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
110 {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
111 {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
112 {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
113 {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
114 {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
115 {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
116 {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
117 {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
118 {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
119 {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
120 {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
121 {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
122 {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
123 {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
124 {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
125 {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
126 {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
127 {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
128 {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
129 {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
130 {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
133 /* Port C: conf, ppar, psor, pdir, podr, pdat */
135 {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
136 {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
137 {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
138 {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
139 {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
140 {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
141 {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
142 {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
143 {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
144 {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
145 {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
146 {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
147 {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
148 {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
149 {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
150 {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
151 {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
152 {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
153 {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
154 {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
155 {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
156 {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
157 {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
158 {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
159 {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
160 {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
161 {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
162 {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
163 {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
164 {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
165 {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
166 {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
169 /* Port D: conf, ppar, psor, pdir, podr, pdat */
171 #ifdef CONFIG_TQM8560
172 {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
173 {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
174 {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
175 #else /* !CONFIG_TQM8560 */
176 {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
177 {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
178 {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
179 #endif /* CONFIG_TQM8560 */
180 {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
181 {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
182 {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
183 {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
184 {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
185 {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
186 {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
187 {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
188 {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
189 {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
190 {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
191 {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
192 {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
193 {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
194 {0, 0, 0, 1, 0, 0}, /* PD14: LED */
195 {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
196 {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
197 {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
198 {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
199 {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
200 {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
201 {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
202 {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
203 {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
204 {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
205 {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
206 {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
207 {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
208 {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
211 #endif /* CONFIG_CPM2 */
213 #define CASL_STRING1 "casl=xx"
214 #define CASL_STRING2 "casl="
216 static const int casl_table[] = { 20, 25, 30 };
217 #define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
219 int cas_latency (void)
221 char *s = getenv ("serial#");
226 casl = CONFIG_DDR_DEFAULT_CL;
229 if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
230 CASL_STRING2, strlen (CASL_STRING2)) == 0) {
231 val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
233 for (i = 0; i < N_CASL; ++i) {
234 if (val == casl_table[i]) {
244 int checkboard (void)
246 char *s = getenv ("serial#");
248 printf ("Board: %s", CONFIG_BOARDNAME);
256 printf ("PCI1: 32 bit, %d MHz (compiled)\n",
257 CONFIG_SYS_CLK_FREQ / 1000000);
259 printf ("PCI1: disabled\n");
263 * Initialize local bus.
270 int misc_init_r (void)
272 volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
275 * Adjust flash start and offset to detected values
277 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
278 gd->bd->bi_flashoffset = 0;
281 * Recalculate CS configuration if second FLASH bank is available
283 if (flash_info[0].size > 0) {
284 memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
285 (CFG_OR1_PRELIM & 0x00007fff);
286 memctl->br1 = gd->bd->bi_flashstart |
287 (CFG_BR1_PRELIM & 0x00007fff);
289 * Re-check to get correct base address for bank 1
291 flash_get_size (gd->bd->bi_flashstart, 0);
298 * If bank 1 is equipped, bank 0 is mapped after bank 1
300 memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
301 (CFG_OR0_PRELIM & 0x00007fff);
302 memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
303 (CFG_BR0_PRELIM & 0x00007fff);
305 * Re-check to get correct base address for bank 0
307 flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
310 * Re-do flash protection upon new addresses
312 flash_protect (FLAG_PROTECT_CLEAR,
313 gd->bd->bi_flashstart, 0xffffffff,
314 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
316 /* Monitor protection ON by default */
317 flash_protect (FLAG_PROTECT_SET,
319 CFG_MONITOR_BASE + monitor_flash_len - 1,
320 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
322 /* Environment protection ON by default */
323 flash_protect (FLAG_PROTECT_SET,
325 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
326 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
328 #ifdef CFG_ENV_ADDR_REDUND
329 /* Redundant environment protection ON by default */
330 flash_protect (FLAG_PROTECT_SET,
332 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
333 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
339 #ifdef CONFIG_CAN_DRIVER
341 * Initialize UPMC RAM
343 static void upmc_write (u_char addr, uint val)
345 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
347 out_be32 (&lbc->mdr, val);
349 clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
350 MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
352 /* dummy access to perform write */
353 out_8 ((void __iomem *)CFG_CAN_BASE, 0);
355 /* normal operation */
356 clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
358 #endif /* CONFIG_CAN_DRIVER */
361 * Initialize Local Bus
363 void local_bus_init (void)
365 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
366 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
374 * Fix Local Bus clock glitch when DLL is enabled.
376 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
377 * If localbus freq is > 133Mhz, DLL can be safely enabled.
378 * Between 66 and 133, the DLL is enabled with an override workaround.
381 get_sys_info (&sysinfo);
382 clkdiv = lbc->lcrr & 0x0f;
383 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
386 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
387 lbc->ltedr = 0xa4c80000; /* DK: !!! */
389 } else if (lbc_hz >= 133) {
390 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
394 * On REV1 boards, need to change CLKDIV before enable DLL.
395 * Default CLKDIV is 8, change it to 4 temporarily.
397 uint pvr = get_pvr ();
398 uint temp_lbcdll = 0;
400 if (pvr == PVR_85xx_REV1) {
401 /* FIXME: Justify the high bit here. */
402 lbc->lcrr = 0x10000004;
405 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
409 * Sample LBC DLL ctrl reg, upshift it to set the
412 temp_lbcdll = gur->lbcdllcr;
413 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
414 asm ("sync;isync;msync");
417 #ifdef CONFIG_CAN_DRIVER
419 * According to timing specifications EAD must be
420 * set if Local Bus Clock is > 83 MHz.
423 out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
425 out_be32 (&lbc->or2, CFG_OR2_CAN);
426 out_be32 (&lbc->br2, CFG_BR2_CAN);
428 /* LGPL4 is UPWAIT */
429 out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
431 /* Initialize UPMC for CAN: single read */
432 upmc_write (0x00, 0xFFFFED00);
433 upmc_write (0x01, 0xCCFFCC00);
434 upmc_write (0x02, 0x00FFCF00);
435 upmc_write (0x03, 0x00FFCF00);
436 upmc_write (0x04, 0x00FFDC00);
437 upmc_write (0x05, 0x00FFCF00);
438 upmc_write (0x06, 0x00FFED00);
439 upmc_write (0x07, 0x3FFFCC07);
441 /* Initialize UPMC for CAN: single write */
442 upmc_write (0x18, 0xFFFFED00);
443 upmc_write (0x19, 0xCCFFEC00);
444 upmc_write (0x1A, 0x00FFED80);
445 upmc_write (0x1B, 0x00FFED80);
446 upmc_write (0x1C, 0x00FFFC00);
447 upmc_write (0x1D, 0x0FFFEC00);
448 upmc_write (0x1E, 0x0FFFEF00);
449 upmc_write (0x1F, 0x3FFFEC05);
450 #endif /* CONFIG_CAN_DRIVER */
453 #if defined(CONFIG_PCI)
455 * Initialize PCI Devices, report devices found.
458 #ifndef CONFIG_PCI_PNP
459 static struct pci_config_table pci_mpc85xxads_config_table[] = {
460 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
461 PCI_IDSEL_NUMBER, PCI_ANY_ID,
462 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
464 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
469 static struct pci_controller hose = {
470 #ifndef CONFIG_PCI_PNP
471 config_table:pci_mpc85xxads_config_table,
475 #endif /* CONFIG_PCI */
477 void pci_init_board (void)
480 pci_mpc85xx_init (&hose);
481 #endif /* CONFIG_PCI */
484 #if defined(CONFIG_OF_BOARD_SETUP)
485 void ft_board_setup (void *blob, bd_t *bd)
490 ft_cpu_setup (blob, bd);
492 node = fdt_path_offset (blob, "/aliases");
496 path = fdt_getprop (blob, node, "pci0", NULL);
498 tmp[1] = hose.last_busno - hose.first_busno;
499 do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
506 #ifdef CONFIG_BOARD_EARLY_INIT_R
507 int board_early_init_r (void)
509 #ifdef CONFIG_PS2MULT
510 ps2mult_early_init ();
511 #endif /* CONFIG_PS2MULT */
514 #endif /* CONFIG_BOARD_EARLY_INIT_R */