3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Copyright 2004 Freescale Semiconductor.
6 * (C) Copyright 2002,2003, Motorola Inc.
7 * Xianghua Xiao, (X.Xiao@motorola.com)
9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/processor.h>
33 #include <asm/immap_85xx.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 extern flash_info_t flash_info[]; /* FLASH chips info */
41 void local_bus_init (void);
42 ulong flash_get_size (ulong base, int banknum);
45 void ps2mult_early_init (void);
50 * I/O Port configuration table
52 * if conf is 1, then that port pin will be configured at boot time
53 * according to the five values podr/pdir/ppar/psor/pdat for that entry
56 const iop_conf_t iop_conf_tab[4][32] = {
58 /* Port A: conf, ppar, psor, pdir, podr, pdat */
60 {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
61 {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
62 {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
63 {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
64 {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
65 {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
66 {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
67 {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
68 {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
69 {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
70 {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
71 {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
72 {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
73 {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
74 {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
75 {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
76 {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
77 {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
78 {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
79 {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
80 {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
81 {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
82 {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
83 {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
84 {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
85 {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
86 {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
87 {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
88 {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
89 {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
90 {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
91 {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
94 /* Port B: conf, ppar, psor, pdir, podr, pdat */
96 {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
97 {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
98 {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
99 {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
100 {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
101 {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
102 {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
103 {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
104 {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
105 {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
106 {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
107 {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
108 {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
109 {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
110 {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
111 {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
112 {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
113 {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
114 {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
115 {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
116 {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
117 {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
118 {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
119 {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
120 {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
121 {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
122 {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
123 {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
124 {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
125 {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
126 {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
127 {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
130 /* Port C: conf, ppar, psor, pdir, podr, pdat */
132 {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
133 {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
134 {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
135 {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
136 {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
137 {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
138 {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
139 {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
140 {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
141 {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
142 {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
143 {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
144 {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
145 {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
146 {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
147 {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
148 {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
149 {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
150 {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
151 {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
152 {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
153 {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
154 {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
155 {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
156 {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
157 {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
158 {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
159 {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
160 {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
161 {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
162 {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
163 {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
166 /* Port D: conf, ppar, psor, pdir, podr, pdat */
168 #ifdef CONFIG_TQM8560
169 {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
170 {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
171 {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
172 #else /* !CONFIG_TQM8560 */
173 {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
174 {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
175 {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
176 #endif /* CONFIG_TQM8560 */
177 {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
178 {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
179 {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
180 {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
181 {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
182 {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
183 {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
184 {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
185 {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
186 {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
187 {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
188 {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
189 {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
190 {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
191 {0, 0, 0, 1, 0, 0}, /* PD14: LED */
192 {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
193 {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
194 {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
195 {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
196 {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
197 {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
198 {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
199 {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
200 {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
201 {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
202 {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
203 {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
204 {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
205 {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
208 #endif /* CONFIG_CPM2 */
210 #define CASL_STRING1 "casl=xx"
211 #define CASL_STRING2 "casl="
213 static const int casl_table[] = { 20, 25, 30 };
214 #define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
216 int cas_latency (void)
218 char *s = getenv ("serial#");
223 casl = CONFIG_DDR_DEFAULT_CL;
226 if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
227 CASL_STRING2, strlen (CASL_STRING2)) == 0) {
228 val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
230 for (i = 0; i < N_CASL; ++i) {
231 if (val == casl_table[i]) {
241 int checkboard (void)
243 char *s = getenv ("serial#");
245 printf ("Board: %s", CONFIG_BOARDNAME);
253 printf ("PCI1: 32 bit, %d MHz (compiled)\n",
254 CONFIG_SYS_CLK_FREQ / 1000000);
256 printf ("PCI1: disabled\n");
260 * Initialize local bus.
267 int misc_init_r (void)
269 volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
272 * Adjust flash start and offset to detected values
274 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
275 gd->bd->bi_flashoffset = 0;
278 * Recalculate CS configuration if second FLASH bank is available
280 if (flash_info[0].size > 0) {
281 memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
282 (CFG_OR1_PRELIM & 0x00007fff);
283 memctl->br1 = gd->bd->bi_flashstart |
284 (CFG_BR1_PRELIM & 0x00007fff);
286 * Re-check to get correct base address for bank 1
288 flash_get_size (gd->bd->bi_flashstart, 0);
295 * If bank 1 is equipped, bank 0 is mapped after bank 1
297 memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
298 (CFG_OR0_PRELIM & 0x00007fff);
299 memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
300 (CFG_BR0_PRELIM & 0x00007fff);
302 * Re-check to get correct base address for bank 0
304 flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
307 * Re-do flash protection upon new addresses
309 flash_protect (FLAG_PROTECT_CLEAR,
310 gd->bd->bi_flashstart, 0xffffffff,
311 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
313 /* Monitor protection ON by default */
314 flash_protect (FLAG_PROTECT_SET,
316 CFG_MONITOR_BASE + monitor_flash_len - 1,
317 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
319 /* Environment protection ON by default */
320 flash_protect (FLAG_PROTECT_SET,
322 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
323 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
325 #ifdef CFG_ENV_ADDR_REDUND
326 /* Redundant environment protection ON by default */
327 flash_protect (FLAG_PROTECT_SET,
329 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
330 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
337 * Initialize Local Bus
339 void local_bus_init (void)
341 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
342 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
350 * Fix Local Bus clock glitch when DLL is enabled.
352 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
353 * If localbus freq is > 133Mhz, DLL can be safely enabled.
354 * Between 66 and 133, the DLL is enabled with an override workaround.
357 get_sys_info (&sysinfo);
358 clkdiv = lbc->lcrr & 0x0f;
359 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
362 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
363 lbc->ltedr = 0xa4c80000; /* DK: !!! */
365 } else if (lbc_hz >= 133) {
366 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
370 * On REV1 boards, need to change CLKDIV before enable DLL.
371 * Default CLKDIV is 8, change it to 4 temporarily.
373 uint pvr = get_pvr ();
374 uint temp_lbcdll = 0;
376 if (pvr == PVR_85xx_REV1) {
377 /* FIXME: Justify the high bit here. */
378 lbc->lcrr = 0x10000004;
381 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
385 * Sample LBC DLL ctrl reg, upshift it to set the
388 temp_lbcdll = gur->lbcdllcr;
389 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
390 asm ("sync;isync;msync");
394 #if defined(CONFIG_PCI)
396 * Initialize PCI Devices, report devices found.
399 #ifndef CONFIG_PCI_PNP
400 static struct pci_config_table pci_mpc85xxads_config_table[] = {
401 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
402 PCI_IDSEL_NUMBER, PCI_ANY_ID,
403 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
405 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
410 static struct pci_controller hose = {
411 #ifndef CONFIG_PCI_PNP
412 config_table:pci_mpc85xxads_config_table,
416 #endif /* CONFIG_PCI */
418 void pci_init_board (void)
421 pci_mpc85xx_init (&hose);
422 #endif /* CONFIG_PCI */
425 #ifdef CONFIG_BOARD_EARLY_INIT_R
426 int board_early_init_r (void)
428 #ifdef CONFIG_PS2MULT
429 ps2mult_early_init ();
430 #endif /* CONFIG_PS2MULT */
433 #endif /* CONFIG_BOARD_EARLY_INIT_R */