2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 extern flash_info_t flash_info[]; /* FLASH chips info */
32 DECLARE_GLOBAL_DATA_PTR;
34 static long int dram_size (long int, long int *, long int);
36 #define _NOT_USED_ 0xFFFFFFFF
38 /* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
39 const uint sdram_table[] =
42 * Single Read. (Offset 0 in UPMA RAM)
44 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
45 0x1FF5FC47, /* last */
47 * SDRAM Initialization (offset 5 in UPMA RAM)
49 * This is no UPM entry point. The following definition uses
50 * the remaining space to establish an initialization
51 * sequence, which is executed by a RUN command.
54 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
56 * Burst Read. (Offset 8 in UPMA RAM)
58 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
59 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
60 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 * Single Write. (Offset 18 in UPMA RAM)
65 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
66 0x1FF5FC47, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_,
69 * Burst Write. (Offset 20 in UPMA RAM)
71 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
72 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 * Refresh (Offset 30 in UPMA RAM)
78 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
79 0xFFFFFC84, 0xFFFFFC07, /* last */
80 _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 * Exception. (Offset 3c in UPMA RAM)
85 0xFFFFFC07, /* last */
86 _NOT_USED_, _NOT_USED_, _NOT_USED_,
89 /* ------------------------------------------------------------------------- */
93 * Check Board Identity:
95 * Test TQ ID string (TQM8xx...)
96 * If present, check for "L" type (no second DRAM bank),
97 * otherwise "L" type is assumed as default.
99 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
102 int checkboard (void)
104 char *s = getenv ("serial#");
108 if (!s || strncmp (s, "TQM8", 4)) {
109 puts ("### No HW ID - assuming TQM8xxL\n");
113 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
114 gd->board_type = 'L';
117 if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
118 gd->board_type = 'M';
121 if ((*(s + 6) == 'D')) { /* a TQM885D type */
122 gd->board_type = 'D';
130 #ifdef CONFIG_VIRTLAB2
131 puts (" (Virtlab2)");
138 /* ------------------------------------------------------------------------- */
140 phys_size_t initdram (int board_type)
142 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
143 volatile memctl8xx_t *memctl = &immap->im_memctl;
144 long int size8, size9, size10;
145 long int size_b0 = 0;
146 long int size_b1 = 0;
148 upmconfig (UPMA, (uint *) sdram_table,
149 sizeof (sdram_table) / sizeof (uint));
152 * Preliminary prescaler for refresh (depends on number of
153 * banks): This value is selected for four cycles every 62.4 us
154 * with two SDRAM banks or four cycles every 31.2 us with one
155 * bank. It will be adjusted after memory sizing.
157 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
160 * The following value is used as an address (i.e. opcode) for
161 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
162 * the port size is 32bit the SDRAM does NOT "see" the lower two
163 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
166 * | | | | +- Burst Length = 4
167 * | | | +----- Burst Type = Sequential
168 * | | +------- CAS Latency = 2
169 * | +----------- Operating Mode = Standard
170 * +-------------- Write Burst Mode = Programmed Burst Length
172 memctl->memc_mar = 0x00000088;
175 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
176 * preliminary addresses - these have to be modified after the
177 * SDRAM size has been determined.
179 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
180 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
182 #ifndef CONFIG_CAN_DRIVER
183 if ((board_type != 'L') &&
184 (board_type != 'M') &&
185 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
186 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
187 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
189 #endif /* CONFIG_CAN_DRIVER */
191 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
195 /* perform SDRAM initializsation sequence */
197 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
199 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
202 #ifndef CONFIG_CAN_DRIVER
203 if ((board_type != 'L') &&
204 (board_type != 'M') &&
205 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
206 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
208 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
211 #endif /* CONFIG_CAN_DRIVER */
213 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
218 * Check Bank 0 Memory Size for re-configuration
222 size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
223 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
230 size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
231 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
235 #if defined(CONFIG_SYS_MAMR_10COL)
239 size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
240 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
243 #endif /* CONFIG_SYS_MAMR_10COL */
245 if ((size8 < size10) && (size9 < size10)) {
247 } else if ((size8 < size9) && (size10 < size9)) {
249 memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
253 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
256 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
258 #ifndef CONFIG_CAN_DRIVER
259 if ((board_type != 'L') &&
260 (board_type != 'M') &&
261 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
263 * Check Bank 1 Memory Size
264 * use current column settings
265 * [9 column SDRAM may also be used in 8 column mode,
266 * but then only half the real size will be used.]
268 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
270 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
274 #endif /* CONFIG_CAN_DRIVER */
279 * Adjust refresh rate depending on SDRAM type, both banks
280 * For types > 128 MBit leave it at the current (fast) rate
282 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
283 /* reduce to 15.6 us (62.4 us / quad) */
284 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
289 * Final mapping: map bigger bank first
291 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
293 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
294 memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
298 * Position Bank 0 immediately above Bank 1
300 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
301 memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
311 memctl->memc_br2 = 0;
313 /* adjust refresh rate depending on SDRAM type, one bank */
314 reg = memctl->memc_mptpr;
315 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
316 memctl->memc_mptpr = reg;
319 } else { /* SDRAM Bank 0 is bigger - map first */
321 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
323 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
327 * Position Bank 1 immediately above Bank 0
330 ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
332 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
337 #ifndef CONFIG_CAN_DRIVER
343 memctl->memc_br3 = 0;
344 #endif /* CONFIG_CAN_DRIVER */
346 /* adjust refresh rate depending on SDRAM type, one bank */
347 reg = memctl->memc_mptpr;
348 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
349 memctl->memc_mptpr = reg;
355 #ifdef CONFIG_CAN_DRIVER
356 /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
358 /* Initialize OR3 / BR3 */
359 memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
360 memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
362 /* Initialize MBMR */
363 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
365 /* Initialize UPMB for CAN: single read */
366 memctl->memc_mdr = 0xFFFFCC04;
367 memctl->memc_mcr = 0x0100 | UPMB;
369 memctl->memc_mdr = 0x0FFFD004;
370 memctl->memc_mcr = 0x0101 | UPMB;
372 memctl->memc_mdr = 0x0FFFC000;
373 memctl->memc_mcr = 0x0102 | UPMB;
375 memctl->memc_mdr = 0x3FFFC004;
376 memctl->memc_mcr = 0x0103 | UPMB;
378 memctl->memc_mdr = 0xFFFFDC07;
379 memctl->memc_mcr = 0x0104 | UPMB;
381 /* Initialize UPMB for CAN: single write */
382 memctl->memc_mdr = 0xFFFCCC04;
383 memctl->memc_mcr = 0x0118 | UPMB;
385 memctl->memc_mdr = 0xCFFCDC04;
386 memctl->memc_mcr = 0x0119 | UPMB;
388 memctl->memc_mdr = 0x3FFCC000;
389 memctl->memc_mcr = 0x011A | UPMB;
391 memctl->memc_mdr = 0xFFFCC004;
392 memctl->memc_mcr = 0x011B | UPMB;
394 memctl->memc_mdr = 0xFFFDC405;
395 memctl->memc_mcr = 0x011C | UPMB;
396 #endif /* CONFIG_CAN_DRIVER */
398 #ifdef CONFIG_ISP1362_USB
399 /* Initialize OR5 / BR5 */
400 memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
401 memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
402 #endif /* CONFIG_ISP1362_USB */
403 return (size_b0 + size_b1);
406 /* ------------------------------------------------------------------------- */
409 * Check memory range for valid RAM. A simple memory test determines
410 * the actually available RAM size between addresses `base' and
411 * `base + maxsize'. Some (not all) hardware errors are detected:
412 * - short between address lines
413 * - short between data lines
416 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
418 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
419 volatile memctl8xx_t *memctl = &immap->im_memctl;
421 memctl->memc_mamr = mamr_value;
423 return (get_ram_size(base, maxsize));
426 /* ------------------------------------------------------------------------- */
428 #ifdef CONFIG_PS2MULT
431 #define BASE_BAUD ( 1843200 / 16 )
432 struct serial_state rs_table[] = {
433 { BASE_BAUD, 4, (void*)0xec140000 },
434 { BASE_BAUD, 2, (void*)0xec150000 },
435 { BASE_BAUD, 6, (void*)0xec160000 },
436 { BASE_BAUD, 10, (void*)0xec170000 },
439 #ifdef CONFIG_BOARD_EARLY_INIT_R
440 int board_early_init_r (void)
442 ps2mult_early_init();
446 #endif /* CONFIG_HMI10 */
448 #endif /* CONFIG_PS2MULT */
451 #ifdef CONFIG_MISC_INIT_R
452 extern void load_sernum_ethaddr(void);
453 int misc_init_r (void)
455 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
456 volatile memctl8xx_t *memctl = &immap->im_memctl;
458 load_sernum_ethaddr();
460 #ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
461 int scy, trlx, flash_or_timing, clk_diff;
463 scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
464 if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
472 * We assume that each 10MHz of bus clock require 1-clk SCY
475 clk_diff = (gd->bus_clk / 1000000) - 50;
478 * We need proper rounding here. This is what the "+5" and "-5"
482 scy += (clk_diff + 5) / 10;
484 scy += (clk_diff - 5) / 10;
487 * For bus frequencies above 50MHz, we want to use relaxed timing
490 if (gd->bus_clk >= 50000000)
503 flash_or_timing = (scy << 4) | trlx |
504 (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
507 flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
510 CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
512 memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
514 debug ("## BR0: 0x%08x OR0: 0x%08x\n",
515 memctl->memc_br0, memctl->memc_or0);
517 if (flash_info[1].size) {
518 #ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
519 memctl->memc_or1 = flash_or_timing |
520 (-flash_info[1].size & 0xFFFF8000);
522 memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
523 (-flash_info[1].size & 0xFFFF8000);
526 ((CONFIG_SYS_FLASH_BASE +
528 size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
530 debug ("## BR1: 0x%08x OR1: 0x%08x\n",
531 memctl->memc_br1, memctl->memc_or1);
533 memctl->memc_br1 = 0; /* invalidate bank */
535 debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
536 memctl->memc_br1, memctl->memc_or1);
539 # ifdef CONFIG_IDE_LED
540 /* Configure PA15 as output port */
541 immap->im_ioport.iop_padir |= 0x0001;
542 immap->im_ioport.iop_paodr |= 0x0001;
543 immap->im_ioport.iop_papar &= ~0x0001;
544 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
548 /* wake up ethernet module */
549 immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
550 immap->im_ioport.iop_pcdir |= 0x0004; /* output */
551 immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
552 immap->im_ioport.iop_pcdat |= 0x0004; /* enable */
553 #endif /* CONFIG_NSCU */
557 #endif /* CONFIG_MISC_INIT_R */
560 # ifdef CONFIG_IDE_LED
561 void ide_led (uchar led, uchar status)
563 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
565 /* We have one led for both pcmcia slots */
566 if (status) { /* led on */
567 immap->im_ioport.iop_padat |= 0x0001;
569 immap->im_ioport.iop_padat &= ~0x0001;
574 #ifdef CONFIG_LCD_INFO
577 #include <timestamp.h>
579 void lcd_show_board_info(void)
583 lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
584 lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
585 lcd_printf (" Wolfgang DENK, wd@denx.de\n");
586 #ifdef CONFIG_LCD_INFO_BELOW_LOGO
587 lcd_printf ("MPC823 CPU at %s MHz\n",
588 strmhz(temp, gd->cpu_clk));
589 lcd_printf (" %ld MB RAM, %ld MB Flash\n",
591 gd->bd->bi_flashsize >> 20 );
593 /* leave one blank line */
594 lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
595 strmhz(temp, gd->cpu_clk),
597 gd->bd->bi_flashsize >> 20 );
598 #endif /* CONFIG_LCD_INFO_BELOW_LOGO */
600 #endif /* CONFIG_LCD_INFO */
602 /* ---------------------------------------------------------------------------- */
603 /* TK885D specific initializaion */
604 /* ---------------------------------------------------------------------------- */
607 int last_stage_init(void)
609 const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
615 /* Without this delay 0xff is read from the UART buffer later in
616 * abortboot() and autoboot is aborted */
618 while (tstc() && i--)
621 /* Check if auto-negotiation is prohibited */
622 s = getenv("phy_auto_nego");
624 if (!s || !strcmp(s, "on"))
625 /* Nothing to do - autonegotiation by default */
628 for (i = 0; i < 2; i++) {
629 ret = miiphy_read("FEC ETHERNET", phy[i], PHY_BMCR, ®);
631 printf("Cannot read BMCR on PHY %d\n", phy[i]);
634 /* Auto-negotiation off, hard set full duplex, 100Mbps */
635 ret = miiphy_write("FEC ETHERNET", phy[i],
636 PHY_BMCR, (reg | PHY_BMCR_100MB |
637 PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON);
639 printf("Cannot write BMCR on PHY %d\n", phy[i]);