2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
35 #if defined(CONFIG_OF_FLAT_TREE)
39 #ifdef CONFIG_VIDEO_SM501
43 #if defined(CONFIG_MPC5200_DDR)
44 #include "mt46v16m16-75.h"
46 #include "mt48lc16m16a2-75.h"
50 void ps2mult_early_init(void);
54 static void sdram_start (int hi_addr)
56 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
58 /* unlock mode register */
59 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
61 __asm__ volatile ("sync");
63 /* precharge all banks */
64 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
66 __asm__ volatile ("sync");
69 /* set mode register: extended mode */
70 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
71 __asm__ volatile ("sync");
73 /* set mode register: reset DLL */
74 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
75 __asm__ volatile ("sync");
78 /* precharge all banks */
79 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
81 __asm__ volatile ("sync");
84 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
86 __asm__ volatile ("sync");
88 /* set mode register */
89 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
90 __asm__ volatile ("sync");
92 /* normal operation */
93 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
94 __asm__ volatile ("sync");
99 * ATTENTION: Although partially referenced initdram does NOT make real use
100 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
101 * is something else than 0x00000000.
104 #if defined(CONFIG_MPC5200)
105 long int initdram (int board_type)
114 /* setup SDRAM chip selects */
115 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
116 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
117 __asm__ volatile ("sync");
119 /* setup config registers */
120 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
121 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
122 __asm__ volatile ("sync");
126 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
127 __asm__ volatile ("sync");
130 /* find RAM size using SDRAM CS0 only */
132 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
134 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
142 /* memory smaller than 1MB is impossible */
143 if (dramsize < (1 << 20)) {
147 /* set SDRAM CS0 size according to the amount of RAM found */
149 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
150 __builtin_ffs(dramsize >> 20) - 1;
152 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
155 /* let SDRAM CS1 start right after CS0 */
156 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
158 /* find RAM size using SDRAM CS1 only */
160 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
162 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
170 /* memory smaller than 1MB is impossible */
171 if (dramsize2 < (1 << 20)) {
175 /* set SDRAM CS1 size according to the amount of RAM found */
177 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
178 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
180 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
183 #else /* CFG_RAMBOOT */
185 /* retrieve size of memory connected to SDRAM CS0 */
186 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
187 if (dramsize >= 0x13) {
188 dramsize = (1 << (dramsize - 0x13)) << 20;
193 /* retrieve size of memory connected to SDRAM CS1 */
194 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
195 if (dramsize2 >= 0x13) {
196 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
200 #endif /* CFG_RAMBOOT */
203 * On MPC5200B we need to set the special configuration delay in the
204 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
205 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
207 * "The SDelay should be written to a value of 0x00000004. It is
208 * required to account for changes caused by normal wafer processing
213 if ((SVR_MJREV(svr) >= 2) &&
214 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
216 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
217 __asm__ volatile ("sync");
220 #if defined(CONFIG_TQM5200_B)
221 return dramsize + dramsize2;
224 #endif /* CONFIG_TQM5200_B */
227 #elif defined(CONFIG_MGT5100)
229 long int initdram (int board_type)
235 /* setup and enable SDRAM chip selects */
236 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
237 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
238 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
239 __asm__ volatile ("sync");
241 /* setup config registers */
242 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
243 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
245 /* address select register */
246 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
247 __asm__ volatile ("sync");
251 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
253 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
261 /* set SDRAM end address according to size */
262 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
264 #else /* CFG_RAMBOOT */
266 /* Retrieve amount of SDRAM available */
267 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
269 #endif /* CFG_RAMBOOT */
275 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
278 int checkboard (void)
280 #if defined(CONFIG_AEVFIFO)
281 puts ("Board: AEVFIFO\n");
285 #if defined(CONFIG_TQM5200S)
286 # define MODULE_NAME "TQM5200S"
288 # define MODULE_NAME "TQM5200"
291 #if defined(CONFIG_STK52XX)
292 # define CARRIER_NAME "STK52xx"
293 #elif defined(CONFIG_TB5200)
294 # define CARRIER_NAME "TB5200"
295 #elif defined(CONFIG_CAM5200)
296 # define CARRIER_NAME "CAM5200"
297 #elif defined(CONFIG_FO300)
298 # define CARRIER_NAME "FO300"
303 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
304 " on a " CARRIER_NAME " carrier board\n");
312 void flash_preinit(void)
315 * Now, when we are in RAM, enable flash write
316 * access for detection process.
317 * Note that CS_BOOT cannot be cleared when
318 * executing in flash.
320 #if defined(CONFIG_MGT5100)
321 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
322 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
324 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
329 static struct pci_controller hose;
331 extern void pci_mpc5xxx_init(struct pci_controller *);
333 void pci_init_board(void)
335 pci_mpc5xxx_init(&hose);
339 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
341 #if defined (CONFIG_MINIFAP)
342 #define SM501_POWER_MODE0_GATE 0x00000040UL
343 #define SM501_POWER_MODE1_GATE 0x00000048UL
344 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
345 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
346 #define SM501_GPIO_DATA_HIGH 0x00010004UL
347 #define SM501_GPIO_51 0x00080000UL
348 #endif /* CONFIG MINIFAP */
350 void init_ide_reset (void)
352 debug ("init_ide_reset\n");
354 #if defined (CONFIG_MINIFAP)
355 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
357 /* enable GPIO control (in both power modes) */
358 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
359 POWER_MODE_GATE_GPIO_PWM_I2C;
360 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
361 POWER_MODE_GATE_GPIO_PWM_I2C;
362 /* configure GPIO51 as output */
363 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
366 /* Configure PSC1_4 as GPIO output for ATA reset */
367 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
368 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
372 void ide_set_reset (int idereset)
374 debug ("ide_reset(%d)\n", idereset);
376 #if defined (CONFIG_MINIFAP)
378 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
381 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
386 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
388 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
392 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
396 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
397 * is left open, no keypress is detected.
399 int post_hotkeys_pressed(void)
401 #ifdef CONFIG_STK52XX
402 struct mpc5xxx_gpio *gpio;
404 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
407 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
408 * CODEC or UART mode. Consumer IrDA should still be possible.
410 gpio->port_config &= ~(0x07000000);
411 gpio->port_config |= 0x03000000;
413 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
414 gpio->simple_gpioe |= 0x20000000;
416 /* Configure GPIO_IRDA_1 as input */
417 gpio->simple_ddr &= ~(0x20000000);
419 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
426 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
428 void post_word_store (ulong a)
430 volatile ulong *save_addr =
431 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
436 ulong post_word_load (void)
438 volatile ulong *save_addr =
439 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
443 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
445 #ifdef CONFIG_PS2MULT
446 #ifdef CONFIG_BOARD_EARLY_INIT_R
447 int board_early_init_r (void)
449 ps2mult_early_init();
453 #endif /* CONFIG_PS2MULT */
456 int silent_boot (void)
458 vu_long timer3_status;
460 /* Configure GPT3 as GPIO input */
461 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
463 /* Read in TIMER_3 pin status */
464 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
466 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
467 /* Force silent console mode if S1 switch
468 * is in closed position (TIMER_3 pin status is LOW). */
469 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
472 /* Force silent console mode if S1 switch
473 * is in open position (TIMER_3 pin status is HIGH). */
474 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
481 int board_early_init_f (void)
483 DECLARE_GLOBAL_DATA_PTR;
486 gd->flags |= GD_FLG_SILENT;
490 #endif /* CONFIG_FO300 */
492 int last_stage_init (void)
495 * auto scan for really existing devices and re-set chip select
502 * Check for SRAM and SRAM size
505 /* save original SRAM content */
506 save = *(volatile u16 *)CFG_CS2_START;
509 /* write test pattern to SRAM */
510 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
511 __asm__ volatile ("sync");
513 * Put a different pattern on the data lines: otherwise they may float
514 * long enough to read back what we wrote.
516 tmp = *(volatile u16 *)CFG_FLASH_BASE;
518 puts ("!! possible error in SRAM detection\n");
520 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
521 /* no SRAM at all, disable cs */
522 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
523 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
524 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
526 __asm__ volatile ("sync");
527 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
528 /* make sure that we access a mirrored address */
529 *(volatile u16 *)CFG_CS2_START = 0x1111;
530 __asm__ volatile ("sync");
531 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
532 /* SRAM size = 512 kByte */
533 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
535 __asm__ volatile ("sync");
536 puts ("SRAM: 512 kB\n");
539 puts ("!! possible error in SRAM detection\n");
541 puts ("SRAM: 1 MB\n");
543 /* restore origianl SRAM content */
545 *(volatile u16 *)CFG_CS2_START = save;
546 __asm__ volatile ("sync");
550 * Check for Grafic Controller
553 /* save origianl FB content */
554 save = *(volatile u16 *)CFG_CS1_START;
557 /* write test pattern to FB memory */
558 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
559 __asm__ volatile ("sync");
561 * Put a different pattern on the data lines: otherwise they may float
562 * long enough to read back what we wrote.
564 tmp = *(volatile u16 *)CFG_FLASH_BASE;
566 puts ("!! possible error in grafic controller detection\n");
568 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
569 /* no grafic controller at all, disable cs */
570 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
571 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
572 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
574 __asm__ volatile ("sync");
576 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
578 /* restore origianl FB content */
580 *(volatile u16 *)CFG_CS1_START = save;
581 __asm__ volatile ("sync");
586 setenv("bootdelay", "0");
594 #ifdef CONFIG_VIDEO_SM501
597 #define DISPLAY_WIDTH 800
599 #define DISPLAY_WIDTH 640
601 #define DISPLAY_HEIGHT 480
603 #ifdef CONFIG_VIDEO_SM501_8BPP
604 #error CONFIG_VIDEO_SM501_8BPP not supported.
605 #endif /* CONFIG_VIDEO_SM501_8BPP */
607 #ifdef CONFIG_VIDEO_SM501_16BPP
608 #error CONFIG_VIDEO_SM501_16BPP not supported.
609 #endif /* CONFIG_VIDEO_SM501_16BPP */
610 #ifdef CONFIG_VIDEO_SM501_32BPP
611 static const SMI_REGS init_regs [] =
615 {0x00048, 0x00021807},
616 {0x0004C, 0x10090a01},
618 {0x00040, 0x00021807},
619 {0x00044, 0x10090a01},
621 {0x80200, 0x00010000},
623 {0x80208, 0x0A000A00},
624 {0x8020C, 0x02fa027f},
625 {0x80210, 0x004a028b},
626 {0x80214, 0x020c01df},
627 {0x80218, 0x000201e9},
628 {0x80200, 0x00013306},
629 #else /* panel + CRT */
632 {0x00048, 0x00021807},
633 {0x0004C, 0x301a0a01},
635 {0x00040, 0x00021807},
636 {0x00044, 0x091a0a01},
638 {0x80000, 0x0f013106},
639 {0x80004, 0xc428bb17},
640 {0x8000C, 0x00000000},
641 {0x80010, 0x0C800C80},
642 {0x80014, 0x03200000},
643 {0x80018, 0x01e00000},
644 {0x8001C, 0x00000000},
645 {0x80020, 0x01e00320},
646 {0x80024, 0x042a031f},
647 {0x80028, 0x0086034a},
648 {0x8002C, 0x020c01df},
649 {0x80030, 0x000201ea},
650 {0x80200, 0x00010000},
653 {0x00048, 0x00021807},
654 {0x0004C, 0x091a0a01},
656 {0x00040, 0x00021807},
657 {0x00044, 0x091a0a01},
659 {0x80000, 0x0f013106},
660 {0x80004, 0xc428bb17},
661 {0x8000C, 0x00000000},
662 {0x80010, 0x0a000a00},
663 {0x80014, 0x02800000},
664 {0x80018, 0x01e00000},
665 {0x8001C, 0x00000000},
666 {0x80020, 0x01e00280},
667 {0x80024, 0x02fa027f},
668 {0x80028, 0x004a028b},
669 {0x8002C, 0x020c01df},
670 {0x80030, 0x000201e9},
671 {0x80200, 0x00010000},
672 #endif /* #ifdef CONFIG_FO300 */
676 #endif /* CONFIG_VIDEO_SM501_32BPP */
678 #ifdef CONFIG_CONSOLE_EXTRA_INFO
680 * Return text to be printed besides the logo.
682 void video_get_info_str (int line_number, char *info)
684 if (line_number == 1) {
685 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
686 #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
687 } else if (line_number == 2) {
688 #if defined (CONFIG_STK52XX)
689 strcpy (info, " on a STK52xx carrier board");
691 #if defined (CONFIG_TB5200)
692 strcpy (info, " on a TB5200 carrier board");
694 #if defined (CONFIG_FO300)
695 strcpy (info, " on a FO300 carrier board");
706 * Returns SM501 register base address. First thing called in the
707 * driver. Checks if SM501 is physically present.
709 unsigned int board_video_init (void)
715 * Check for Grafic Controller
718 /* save origianl FB content */
719 save = *(volatile u16 *)CFG_CS1_START;
722 /* write test pattern to FB memory */
723 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
724 __asm__ volatile ("sync");
726 * Put a different pattern on the data lines: otherwise they may float
727 * long enough to read back what we wrote.
729 tmp = *(volatile u16 *)CFG_FLASH_BASE;
731 puts ("!! possible error in grafic controller detection\n");
733 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
734 /* no grafic controller found */
738 ret = SM501_MMIO_BASE;
742 *(volatile u16 *)CFG_CS1_START = save;
743 __asm__ volatile ("sync");
749 * Returns SM501 framebuffer address
751 unsigned int board_video_get_fb (void)
753 return SM501_FB_BASE;
757 * Called after initializing the SM501 and before clearing the screen.
759 void board_validate_screen (unsigned int base)
764 * Return a pointer to the initialization sequence.
766 const SMI_REGS *board_get_regs (void)
771 int board_get_width (void)
773 return DISPLAY_WIDTH;
776 int board_get_height (void)
778 return DISPLAY_HEIGHT;
781 #endif /* CONFIG_VIDEO_SM501 */
783 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
784 void ft_board_setup(void *blob, bd_t *bd)
786 ft_cpu_setup(blob, bd);
788 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */