2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
35 #ifdef CONFIG_VIDEO_SM501
39 #if defined(CONFIG_MPC5200_DDR)
40 #include "mt46v16m16-75.h"
42 #include "mt48lc16m16a2-75.h"
46 void ps2mult_early_init(void);
50 static void sdram_start (int hi_addr)
52 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
54 /* unlock mode register */
55 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
57 __asm__ volatile ("sync");
59 /* precharge all banks */
60 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
62 __asm__ volatile ("sync");
65 /* set mode register: extended mode */
66 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
67 __asm__ volatile ("sync");
69 /* set mode register: reset DLL */
70 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
71 __asm__ volatile ("sync");
74 /* precharge all banks */
75 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
77 __asm__ volatile ("sync");
80 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
82 __asm__ volatile ("sync");
84 /* set mode register */
85 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
86 __asm__ volatile ("sync");
88 /* normal operation */
89 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
90 __asm__ volatile ("sync");
95 * ATTENTION: Although partially referenced initdram does NOT make real use
96 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
97 * is something else than 0x00000000.
100 #if defined(CONFIG_MPC5200)
101 long int initdram (int board_type)
110 /* setup SDRAM chip selects */
111 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
112 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
113 __asm__ volatile ("sync");
115 /* setup config registers */
116 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
117 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
118 __asm__ volatile ("sync");
122 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
123 __asm__ volatile ("sync");
126 /* find RAM size using SDRAM CS0 only */
128 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
130 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
138 /* memory smaller than 1MB is impossible */
139 if (dramsize < (1 << 20)) {
143 /* set SDRAM CS0 size according to the amount of RAM found */
145 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
146 __builtin_ffs(dramsize >> 20) - 1;
148 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
151 /* let SDRAM CS1 start right after CS0 */
152 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
154 /* find RAM size using SDRAM CS1 only */
156 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
158 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
166 /* memory smaller than 1MB is impossible */
167 if (dramsize2 < (1 << 20)) {
171 /* set SDRAM CS1 size according to the amount of RAM found */
173 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
174 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
176 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
179 #else /* CFG_RAMBOOT */
181 /* retrieve size of memory connected to SDRAM CS0 */
182 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
183 if (dramsize >= 0x13) {
184 dramsize = (1 << (dramsize - 0x13)) << 20;
189 /* retrieve size of memory connected to SDRAM CS1 */
190 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
191 if (dramsize2 >= 0x13) {
192 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
196 #endif /* CFG_RAMBOOT */
199 * On MPC5200B we need to set the special configuration delay in the
200 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
201 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
203 * "The SDelay should be written to a value of 0x00000004. It is
204 * required to account for changes caused by normal wafer processing
209 if ((SVR_MJREV(svr) >= 2) &&
210 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
212 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
213 __asm__ volatile ("sync");
216 #if defined(CONFIG_TQM5200_B)
217 return dramsize + dramsize2;
220 #endif /* CONFIG_TQM5200_B */
223 #elif defined(CONFIG_MGT5100)
225 long int initdram (int board_type)
231 /* setup and enable SDRAM chip selects */
232 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
233 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
234 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
235 __asm__ volatile ("sync");
237 /* setup config registers */
238 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
239 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
241 /* address select register */
242 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
243 __asm__ volatile ("sync");
247 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
249 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
257 /* set SDRAM end address according to size */
258 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
260 #else /* CFG_RAMBOOT */
262 /* Retrieve amount of SDRAM available */
263 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
265 #endif /* CFG_RAMBOOT */
271 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
274 int checkboard (void)
276 #if defined(CONFIG_AEVFIFO)
277 puts ("Board: AEVFIFO\n");
281 #if defined(CONFIG_TQM5200S)
282 # define MODULE_NAME "TQM5200S"
284 # define MODULE_NAME "TQM5200"
287 #if defined(CONFIG_STK52XX)
288 # define CARRIER_NAME "STK52xx"
289 #elif defined(CONFIG_TB5200)
290 # define CARRIER_NAME "TB5200"
291 #elif defined(CONFIG_CAM5200)
292 # define CARRIER_NAME "Cam5200"
293 #elif defined(CONFIG_FO300)
294 # define CARRIER_NAME "FO300"
299 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
300 " on a " CARRIER_NAME " carrier board\n");
308 void flash_preinit(void)
311 * Now, when we are in RAM, enable flash write
312 * access for detection process.
313 * Note that CS_BOOT cannot be cleared when
314 * executing in flash.
316 #if defined(CONFIG_MGT5100)
317 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
318 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
320 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
325 static struct pci_controller hose;
327 extern void pci_mpc5xxx_init(struct pci_controller *);
329 void pci_init_board(void)
331 pci_mpc5xxx_init(&hose);
335 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
337 #if defined (CONFIG_MINIFAP)
338 #define SM501_POWER_MODE0_GATE 0x00000040UL
339 #define SM501_POWER_MODE1_GATE 0x00000048UL
340 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
341 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
342 #define SM501_GPIO_DATA_HIGH 0x00010004UL
343 #define SM501_GPIO_51 0x00080000UL
345 #define GPIO_PSC1_4 0x01000000UL
348 void init_ide_reset (void)
350 debug ("init_ide_reset\n");
352 #if defined (CONFIG_MINIFAP)
353 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
355 /* enable GPIO control (in both power modes) */
356 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
357 POWER_MODE_GATE_GPIO_PWM_I2C;
358 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
359 POWER_MODE_GATE_GPIO_PWM_I2C;
360 /* configure GPIO51 as output */
361 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
364 /* Configure PSC1_4 as GPIO output for ATA reset */
365 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
366 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
370 void ide_set_reset (int idereset)
372 debug ("ide_reset(%d)\n", idereset);
374 #if defined (CONFIG_MINIFAP)
376 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
379 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
384 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
386 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
390 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
394 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
395 * is left open, no keypress is detected.
397 int post_hotkeys_pressed(void)
399 struct mpc5xxx_gpio *gpio;
401 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
404 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
405 * CODEC or UART mode. Consumer IrDA should still be possible.
407 gpio->port_config &= ~(0x07000000);
408 gpio->port_config |= 0x03000000;
410 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
411 gpio->simple_gpioe |= 0x20000000;
413 /* Configure GPIO_IRDA_1 as input */
414 gpio->simple_ddr &= ~(0x20000000);
416 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
420 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
422 void post_word_store (ulong a)
424 volatile ulong *save_addr =
425 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
430 ulong post_word_load (void)
432 volatile ulong *save_addr =
433 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
437 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
439 #ifdef CONFIG_PS2MULT
440 #ifdef CONFIG_BOARD_EARLY_INIT_R
441 int board_early_init_r (void)
443 ps2mult_early_init();
447 #endif /* CONFIG_PS2MULT */
450 int silent_boot (void)
452 vu_long timer3_status;
454 /* Configure GPT3 as GPIO input */
455 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
457 /* Read in TIMER_3 pin status */
458 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
460 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
461 /* Force silent console mode if S1 switch
462 * is in closed position (TIMER_3 pin status is LOW). */
463 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
466 /* Force silent console mode if S1 switch
467 * is in open position (TIMER_3 pin status is HIGH). */
468 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
475 int board_early_init_f (void)
477 DECLARE_GLOBAL_DATA_PTR;
480 gd->flags |= GD_FLG_SILENT;
484 #endif /* CONFIG_FO300 */
486 int last_stage_init (void)
489 * auto scan for really existing devices and re-set chip select
496 * Check for SRAM and SRAM size
499 /* save original SRAM content */
500 save = *(volatile u16 *)CFG_CS2_START;
503 /* write test pattern to SRAM */
504 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
505 __asm__ volatile ("sync");
507 * Put a different pattern on the data lines: otherwise they may float
508 * long enough to read back what we wrote.
510 tmp = *(volatile u16 *)CFG_FLASH_BASE;
512 puts ("!! possible error in SRAM detection\n");
514 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
515 /* no SRAM at all, disable cs */
516 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
517 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
518 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
520 __asm__ volatile ("sync");
521 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
522 /* make sure that we access a mirrored address */
523 *(volatile u16 *)CFG_CS2_START = 0x1111;
524 __asm__ volatile ("sync");
525 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
526 /* SRAM size = 512 kByte */
527 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
529 __asm__ volatile ("sync");
530 puts ("SRAM: 512 kB\n");
533 puts ("!! possible error in SRAM detection\n");
535 puts ("SRAM: 1 MB\n");
537 /* restore origianl SRAM content */
539 *(volatile u16 *)CFG_CS2_START = save;
540 __asm__ volatile ("sync");
544 * Check for Grafic Controller
547 /* save origianl FB content */
548 save = *(volatile u16 *)CFG_CS1_START;
551 /* write test pattern to FB memory */
552 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
553 __asm__ volatile ("sync");
555 * Put a different pattern on the data lines: otherwise they may float
556 * long enough to read back what we wrote.
558 tmp = *(volatile u16 *)CFG_FLASH_BASE;
560 puts ("!! possible error in grafic controller detection\n");
562 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
563 /* no grafic controller at all, disable cs */
564 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
565 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
566 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
568 __asm__ volatile ("sync");
570 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
572 /* restore origianl FB content */
574 *(volatile u16 *)CFG_CS1_START = save;
575 __asm__ volatile ("sync");
580 setenv("bootdelay", "0");
588 #ifdef CONFIG_VIDEO_SM501
591 #define DISPLAY_WIDTH 800
593 #define DISPLAY_WIDTH 640
595 #define DISPLAY_HEIGHT 480
597 #ifdef CONFIG_VIDEO_SM501_8BPP
598 #error CONFIG_VIDEO_SM501_8BPP not supported.
599 #endif /* CONFIG_VIDEO_SM501_8BPP */
601 #ifdef CONFIG_VIDEO_SM501_16BPP
602 #error CONFIG_VIDEO_SM501_16BPP not supported.
603 #endif /* CONFIG_VIDEO_SM501_16BPP */
604 #ifdef CONFIG_VIDEO_SM501_32BPP
605 static const SMI_REGS init_regs [] =
609 {0x00048, 0x00021807},
610 {0x0004C, 0x10090a01},
612 {0x00040, 0x00021807},
613 {0x00044, 0x10090a01},
615 {0x80200, 0x00010000},
617 {0x80208, 0x0A000A00},
618 {0x8020C, 0x02fa027f},
619 {0x80210, 0x004a028b},
620 {0x80214, 0x020c01df},
621 {0x80218, 0x000201e9},
622 {0x80200, 0x00013306},
623 #else /* panel + CRT */
626 {0x00048, 0x00021807},
627 {0x0004C, 0x301a0a01},
629 {0x00040, 0x00021807},
630 {0x00044, 0x091a0a01},
632 {0x80000, 0x0f013106},
633 {0x80004, 0xc428bb17},
634 {0x8000C, 0x00000000},
635 {0x80010, 0x0C800C80},
636 {0x80014, 0x03200000},
637 {0x80018, 0x01e00000},
638 {0x8001C, 0x00000000},
639 {0x80020, 0x01e00320},
640 {0x80024, 0x042a031f},
641 {0x80028, 0x0086034a},
642 {0x8002C, 0x020c01df},
643 {0x80030, 0x000201ea},
644 {0x80200, 0x00010000},
647 {0x00048, 0x00021807},
648 {0x0004C, 0x091a0a01},
650 {0x00040, 0x00021807},
651 {0x00044, 0x091a0a01},
653 {0x80000, 0x0f013106},
654 {0x80004, 0xc428bb17},
655 {0x8000C, 0x00000000},
656 {0x80010, 0x0a000a00},
657 {0x80014, 0x02800000},
658 {0x80018, 0x01e00000},
659 {0x8001C, 0x00000000},
660 {0x80020, 0x01e00280},
661 {0x80024, 0x02fa027f},
662 {0x80028, 0x004a028b},
663 {0x8002C, 0x020c01df},
664 {0x80030, 0x000201e9},
665 {0x80200, 0x00010000},
666 #endif /* #ifdef CONFIG_FO300 */
670 #endif /* CONFIG_VIDEO_SM501_32BPP */
672 #ifdef CONFIG_CONSOLE_EXTRA_INFO
674 * Return text to be printed besides the logo.
676 void video_get_info_str (int line_number, char *info)
678 if (line_number == 1) {
679 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
680 #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
681 } else if (line_number == 2) {
682 #if defined (CONFIG_STK52XX)
683 strcpy (info, " on a STK52xx carrier board");
685 #if defined (CONFIG_TB5200)
686 strcpy (info, " on a TB5200 carrier board");
688 #if defined (CONFIG_FO300)
689 strcpy (info, " on a FO300 carrier board");
700 * Returns SM501 register base address. First thing called in the
701 * driver. Checks if SM501 is physically present.
703 unsigned int board_video_init (void)
709 * Check for Grafic Controller
712 /* save origianl FB content */
713 save = *(volatile u16 *)CFG_CS1_START;
716 /* write test pattern to FB memory */
717 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
718 __asm__ volatile ("sync");
720 * Put a different pattern on the data lines: otherwise they may float
721 * long enough to read back what we wrote.
723 tmp = *(volatile u16 *)CFG_FLASH_BASE;
725 puts ("!! possible error in grafic controller detection\n");
727 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
728 /* no grafic controller found */
732 ret = SM501_MMIO_BASE;
736 *(volatile u16 *)CFG_CS1_START = save;
737 __asm__ volatile ("sync");
743 * Returns SM501 framebuffer address
745 unsigned int board_video_get_fb (void)
747 return SM501_FB_BASE;
751 * Called after initializing the SM501 and before clearing the screen.
753 void board_validate_screen (unsigned int base)
758 * Return a pointer to the initialization sequence.
760 const SMI_REGS *board_get_regs (void)
765 int board_get_width (void)
767 return DISPLAY_WIDTH;
770 int board_get_height (void)
772 return DISPLAY_HEIGHT;
775 #endif /* CONFIG_VIDEO_SM501 */