2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_MPC5200_DDR)
35 #include "mt46v16m16-75.h"
37 #include "mt48lc16m16a2-75.h"
41 static void sdram_start (int hi_addr)
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
45 /* unlock mode register */
46 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
48 __asm__ volatile ("sync");
50 /* precharge all banks */
51 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
53 __asm__ volatile ("sync");
56 /* set mode register: extended mode */
57 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
58 __asm__ volatile ("sync");
60 /* set mode register: reset DLL */
61 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
62 __asm__ volatile ("sync");
65 /* precharge all banks */
66 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
68 __asm__ volatile ("sync");
71 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
73 __asm__ volatile ("sync");
75 /* set mode register */
76 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
77 __asm__ volatile ("sync");
79 /* normal operation */
80 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
81 __asm__ volatile ("sync");
86 * ATTENTION: Although partially referenced initdram does NOT make real use
87 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
88 * is something else than 0x00000000.
91 #if defined(CONFIG_MPC5200)
92 long int initdram (int board_type)
99 /* setup SDRAM chip selects */
100 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
101 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
102 __asm__ volatile ("sync");
104 /* setup config registers */
105 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
106 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
107 __asm__ volatile ("sync");
111 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
112 __asm__ volatile ("sync");
115 /* find RAM size using SDRAM CS0 only */
117 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
119 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
127 /* memory smaller than 1MB is impossible */
128 if (dramsize < (1 << 20)) {
132 /* set SDRAM CS0 size according to the amount of RAM found */
134 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
135 __builtin_ffs(dramsize >> 20) - 1;
137 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
140 /* let SDRAM CS1 start right after CS0 */
141 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
143 /* find RAM size using SDRAM CS1 only */
145 test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
147 test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
155 /* memory smaller than 1MB is impossible */
156 if (dramsize2 < (1 << 20)) {
160 /* set SDRAM CS1 size according to the amount of RAM found */
162 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
163 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
165 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
168 #else /* CFG_RAMBOOT */
170 /* retrieve size of memory connected to SDRAM CS0 */
171 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
172 if (dramsize >= 0x13) {
173 dramsize = (1 << (dramsize - 0x13)) << 20;
178 /* retrieve size of memory connected to SDRAM CS1 */
179 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
180 if (dramsize2 >= 0x13) {
181 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
186 #endif /* CFG_RAMBOOT */
188 /* return dramsize + dramsize2; */
192 #elif defined(CONFIG_MGT5100)
194 long int initdram (int board_type)
200 /* setup and enable SDRAM chip selects */
201 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
202 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
203 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
204 __asm__ volatile ("sync");
206 /* setup config registers */
207 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
208 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
210 /* address select register */
211 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
212 __asm__ volatile ("sync");
216 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
218 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
226 /* set SDRAM end address according to size */
227 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
229 #else /* CFG_RAMBOOT */
231 /* Retrieve amount of SDRAM available */
232 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
234 #endif /* CFG_RAMBOOT */
240 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
243 int checkboard (void)
245 #if defined (CONFIG_TQM5200_AA)
246 puts ("Board: TQM5200-AA (TQ-Systems GmbH)\n");
248 #if defined (CONFIG_TQM5200_AB)
249 puts ("Board: TQM5200-AB (TQ-Systems GmbH)\n");
251 #if defined (CONFIG_TQM5200_AC)
252 puts ("Board: TQM5200-AC (TQ-Systems GmbH)\n");
257 void flash_preinit(void)
260 * Now, when we are in RAM, enable flash write
261 * access for detection process.
262 * Note that CS_BOOT cannot be cleared when
263 * executing in flash.
265 #if defined(CONFIG_MGT5100)
266 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
267 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
269 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
274 static struct pci_controller hose;
276 extern void pci_mpc5xxx_init(struct pci_controller *);
278 void pci_init_board(void)
280 pci_mpc5xxx_init(&hose);
284 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
286 #if defined (CONFIG_MINIFAP)
287 #define SM501_POWER_MODE0_GATE 0x00000040UL
288 #define SM501_POWER_MODE1_GATE 0x00000048UL
289 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
290 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
291 #define SM501_GPIO_DATA_HIGH 0x00010004UL
292 #define SM501_GPIO_51 0x00080000UL
294 #define GPIO_PSC1_4 0x01000000UL
297 void init_ide_reset (void)
299 debug ("init_ide_reset\n");
301 #if defined (CONFIG_MINIFAP)
302 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
304 /* enable GPIO control (in both power modes) */
305 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
306 POWER_MODE_GATE_GPIO_PWM_I2C;
307 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
308 POWER_MODE_GATE_GPIO_PWM_I2C;
309 /* configure GPIO51 as output */
310 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
313 /* Configure PSC1_4 as GPIO output for ATA reset */
314 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
315 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
319 void ide_set_reset (int idereset)
321 debug ("ide_reset(%d)\n", idereset);
323 #if defined (CONFIG_MINIFAP)
325 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
328 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
333 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
335 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
339 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
343 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
344 * is left open, no keypress is detected.
346 int post_hotkeys_pressed(void)
348 struct mpc5xxx_gpio *gpio;
350 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
353 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
354 * CODEC or UART mode. Consumer IrDA should still be possible.
356 gpio->port_config &= ~(0x07000000);
357 gpio->port_config |= 0x03000000;
359 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
360 gpio->simple_gpioe |= 0x20000000;
362 /* Configure GPIO_IRDA_1 as input */
363 gpio->simple_ddr &= ~(0x20000000);
365 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
369 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
371 void post_word_store (ulong a)
373 volatile ulong *save_addr =
374 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
379 ulong post_word_load (void)
381 volatile ulong *save_addr =
382 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
387 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/